1 / 16

Up and Down Counter with a Seven Segment Display Encoder

Part 1. Implementing Sequential Logic in VHDL. Up and Down Counter with a Seven Segment Display Encoder. S6. S5. S4. S3. S2. S1. S0. DP. Block diagram of the counter. Experiment 2 Problem 1 Pseudo-Random Number Generator. Linear Feedback Shift Register (LFSR).

turi
Download Presentation

Up and Down Counter with a Seven Segment Display Encoder

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. Part 1 Implementing Sequential Logic in VHDL Up and Down Counter with a Seven Segment Display Encoder

  2. S6 S5 S4 S3 S2 S1 S0 DP

  3. Block diagram of the counter

  4. Experiment 2 Problem 1 Pseudo-Random Number Generator

  5. Linear Feedback Shift Register (LFSR) Each stage = D flip-flop  L, C(D)  Length Connection polynomial, C(D) C(D) = 1 + c1D + c2D2 + . . . + cLDL

  6. Sj-1 Sj-2 Sj-(L-1) Sj-L Initial state [sL-1, sL-2, . . . , s1, s0] LSFR recursion: sj = c1sj-1 c2sj-2 . . .  cL-1sj-(L-1) cLsj-L for j  L

  7. Example of LFSR  4, 1+D+D4 Length Connection polynomial, C(D) C(D) = 1 + 1D + 0D2 + 0D3 +1D4 c1=1 c2=0 c4=1 c3=0

  8. LFSR State Sequence s4 s3 s2 s1 s0 s4 = c1s3c2s2 c3s1  c4s0 = s3 s0

  9. seed coeff 4 4 load_coeff init_run PRNG strobe ext_clk strobe_divclk 7 current_state

  10. D D D D Q Q Q Q Regular Shift Register Q(1) Q(0) Q(2) Q(3) Sin Clock Enable Hint: Use similar techniques for clocking and enabling LFSR

  11. D D D D Q Q Q Q Initializing Serial Shift Register with Parallel Load Load D(3) D(2) D(1) D(0) Sin Clock Enable Q(3) Q(2) Q(1) Q(0) Hint: Use similar technique for initializing LFSR

  12. Experiment 2 Problem 2 One-Hex-Digit Calculator

  13. operand 4 3 operation code One-hex-digit calculator strobe 7 output

  14. Operations operation_code : operation 1 : ADD 2: SUB 4: AND 5: OR 6: XOR 7 : MUL (bonus)

  15. Sequence of actions a. display output blank b. operation code read and displayed on a seven segment display c. operand 1 read and displayed on a seven segment display d. operand 2 read and displayed on a seven segment display e. result calculated and displayed on a seven segment display f. go to step a.

More Related