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Computer Organization

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  1. Unit III & IV : Input/output Organization Computer Organization Department of CSE, SSE Mukka www.bookspar.com | Website for students | VTU NOTES

  2. Accessing I/O Devices • A simple arrangement to connect I/O devices to a computer it to use a single bus arrangement • The bus enables all the devices connected to it to exchange information • Bus consists of 3 sets of lines to carry address, data and control signals. • Each I/O device is assigned a unique set of addresses • When processor places address on the bus, the device that recognises this address responds to the commands issued on the control lines. • When I/O devices and memory share the same address space, the arrangement is called as memory-mapped I/O www.bookspar.com | Website for students | VTU NOTES

  3. Processor Memory Bus I/O de vice 1 I/O de vice n Figure 4.1. A single-bus structure. www.bookspar.com | Website for students | VTU NOTES

  4. Accessing I/O Devices • With memory-mapped I/O, any machine instruction that can access memory can be used to transfer data to or from an I/O device. • Eg., if DATAIN is input buffer associated with keyboard, • Move DATAIN, R0 reads data from DATAIN and stores into processor register R0 • Move R0,DATAOUT sends contents of R0 to location DATAOUT, which may be output data buffer www.bookspar.com | Website for students | VTU NOTES

  5. Contd… • When I/O devices and memory share different address space, the arrangement is called as I/O-mapped I/O. • E.g., Processors like Intel Family, have separate In and Out instructions to perform I/O transfers • One advantage of a separate I/O address space is I/O devices deal with a fewer address lines. • I/O address lines need not be separate from memory address lines even if there are separate instructions for I/O • In such cases a special signal on the bus indicates that it is an I/O operation. Memory ignores the requested transfer. • The I/O devices examine the low-order bits of the address bus to determine whether they should respond. www.bookspar.com | Website for students | VTU NOTES

  6. Hardware devices required to connect an I/O device to the bus www.bookspar.com | Website for students | VTU NOTES

  7. I/O interface • Address decoder – enables the device to recognize its address when this address appears on address lines • The data register holds the data being transferred to/from the processor • The status register contains information relevant to the operation of the I/O device • Both the data and status registers are connected to the data bus and assigned unique addresses • The address decoder, the data and the status registers, and the control circuitry required to coordinate I/O transfers constitute the device’s interface circuit www.bookspar.com | Website for students | VTU NOTES

  8. D A T AIN D A T A OUT KIRQ SOUT SIN ST A TUS DIRQ KEN CONTR OL DEN 7 6 5 4 3 2 1 0 Registers in keyboard and display interfaces Figure 4.3. KIRQ and DIRQ are associated with interrupts www.bookspar.com | Website for students | VTU NOTES

  9. Mo v e #LINE,R0 Initialize memory pointer W AITK T estBit #0,ST A TUS T est SIN. Branc h=0 W AITK W ait for c haracter to b e en tered. Mo v e D A T AIN,R1 Read c haracter. W AITD T estBit #1,ST A TUS T est SOUT. Branc h=0 W AITD W ait for displa y to b ecome ready . Mo v e R1,D A T A OUT Send c haracter to displa y . Mo v e R1,(R0)+ Store c haracter and adv ance p oin ter. Compare #$0D,R1 Chec k if Carriage Return. Branc h 0 W AITK If not, get another c haracter. Mo v e #$0A,D A T A OUT Otherwise, send Line F eed. Call PR OCESS Call a subroutine to pro cess the input line. Figure 4.4 A program that reads one line from the keyboard stores it in memory buffer, and echoes it back to the display. www.bookspar.com | Website for students | VTU NOTES

  10. 3 mechanisms of implementing I/O operations • Program controlled I/O • Processor repeatedly checks a status flag to achieve the required synchronization between the processor and an input or output device • Processor polls the device • Using Interrupts • Where the device lets the processor know that it is ready • Direct memory access • For fast I/O transfers www.bookspar.com | Website for students | VTU NOTES

  11. INTERRUPTS • In the previous example we discussed, the program enters wait loop, in which it repeatedly tests the device status. • During this process, the processor is not performing any useful computation • There are many situations where other tasks can be performed while waiting for I/O device to become ready • So instead, I/O device will alert the processor when it is ready. It does so by sending an hardware signal called as interrupt • One of the bus control lines, called an interrupt-request line, is usually dedicated for this purpose. • Hence processor can use waiting time to perform other useful activities • Eliminate the waiting period by using interrupts www.bookspar.com | Website for students | VTU NOTES

  12. Example • Consider a task that requires some computations to be performed and the results to be printed on a line printer. Followed by more computations and output. Let the program consists of two routines, COMPUTE and PRINT COMPUTE produces n-lines of output to be printed by PRINT routine. • Can perform this in different ways • Repeatedly executing first COMPUTE routine and then PRINT routine • Printer accepts only one line at a time. Hence, PRINT routine must send one line of text, wait for it to be printed, then send the next line and so on. • Disadvantage of this technique is that processor spends a considerable amount of time waiting for the printer to become ready • Overlap printing and computation • To execute COMPUTE routine while the printing is in progress. • How to achieve? www.bookspar.com | Website for students | VTU NOTES

  13. COMPUTE routine is executed to produce n lines of output. • PRINT routine executed to send the first line of text to the printer. • Instead of waiting for this line to be printed, PRINT routine is temporarily suspended and execution of COMPUTE routine continued. • Whenever the printer becomes ready, it alerts the processor by sending interrupt-request signal. • The processor interrupts the execution of COMPUTE routine and transfers control to PRINT routine and the process is repeated • If COMPUTE routine takes a longer time to generate n lines than the time required by PRINT routine to print them, the processor will be performing useful computations all the time. www.bookspar.com | Website for students | VTU NOTES

  14. www.bookspar.com | Website for students | VTU NOTES

  15. Interrupts contd.. • The routine executed in response to an interrupt request is called the interrupt-service routine. • In prev example, it was PRINT routine • Interrupts bears considerable resemblance with subroutine calls • Assume that an interrupt request arrives when the processor is processing ith instruction of COMPUTE routine. • Processor first completes execution of ith instruction and loads the PC address with the address of the first instruction of the interrupt service routine • After execution of the interrupt service routine, the processor has to come back to instruction i+1. • So when an interrupt occurs, the current contents of PC must be kept in a temporary storage location • A return from interrupt instruction will reload the PC with the contents of this temporary storage location, causing execution to resume at instruction i+1 • in many processors return address is saved in processor stack. www.bookspar.com | Website for students | VTU NOTES

  16. Contd.. • The processor must let the device know that its interrupt request has been acknowledged. • So that it removes its interrupt request signal • This can be accomplished by a special control signal on control bus called as interrupt-acknowledge signal. • An alternative to accomplish this is to have transfer of data between processor and I/O device interface • The execution of an instruction in the interrupt service routine that accesses a status or data register in the device interface implicitly informs the device that its interrupt request has been recognized. www.bookspar.com | Website for students | VTU NOTES

  17. Difference between an interrupt service routine and Subroutine • A subroutine performs a function required by the program from which it is called. • An interrupt service routine may not have anything in common with the program being executed at the time interrupt request is received. • Often it belongs to 2 different users. • Therefore before starting execution of ISR ( Interrupt service routine), any information that may be altered during the execution of interrupt must be saved. • This information must be restored before execution of interrupted program is resumed. • This information typically includes the condition code flags and the contents of any registers used by both the interrupted program and the interrupt-service routine. www.bookspar.com | Website for students | VTU NOTES

  18. Interrupt latency • The task of saving and restoring information is done automatically by processor or by program instructions • Most modern processors save only the minimum amount of information needed to maintain the integrity of program execution • Because the process of saving and restoring registers involves memory transfers that increase total execution time ( execution overhead ) • Saving registers increases the delay between the time interrupt request is received and the start of execution of interrupt-service routine. This delay is called as interrupt latency • In some applications, longer interrupt latency is unacceptable. • Hence keep the amount of information, saved automatically by the processor when an interrupt request is accepted, to a minimum. • Typically processor saves only the PC and the processor status register • Any additional info to be saved must be saved by the program instructions at the beginning of the interrupt-service routine and restored at the end of the routine www.bookspar.com | Website for students | VTU NOTES

  19. Registers retrieval • Some processor with small no of registers saves automatically all processor registers automatically at the time an interrupt request is accepted • Some computers provide 2 types of instructions • One saves all processor registers • Other does not ( may save only part ) • Another approach is to provide duplicate set of processor registers • Another set of registers used by interrupt service routine, hence no need to save and restore processor registers www.bookspar.com | Website for students | VTU NOTES

  20. Usage of interrupts • Interrupts is used not only for I/O transfers • It allows transfer of control from one program to another due to an event external to the computer • Concept of interrupts is used in OS • Also in many control applications where processing of certain routines must be accurately timed relative to external events. • Called as real-time processing www.bookspar.com | Website for students | VTU NOTES

  21. Interrupt hardware • An I/O device requests an interrupt by activating a bus line called interrupt-request. • Following diagram shows how a single interrupt-request line may be used to serve n devices. • All devices connected to the line via switches to the ground. To request an interrupt, a device closes its associated switch. • When a device requests an interrupt by closing its switch, the voltage on the line drops to 0, causing the interrupt-request signal, INTR, received by the processor to go to 1. • Value of INTR is the logical OR of the requests from individual devices • INTR = INTR1 + … + INTRn www.bookspar.com | Website for students | VTU NOTES

  22. V dd Pull up resistor Processor R I N T R INTR INTR1 INTR2 INTR n Figure 4.6. An equivalent circuit for an open-drain bus used to implement a common interrupt-request line. www.bookspar.com | Website for students | VTU NOTES

  23. Enabling and disabling interrupts • Interruption of the program execution due to arrival of interrupts must be carefully controlled • So in all computers there will be facility to enable and disable interrupts as desired • There are many situations where in processor should ignore interrupt requests. • For eg., in the compute-print program, an interrupt request from the printer should be accepted only if there are output lines to be printed • Simplest way is to provide machine instructions like Interrupt-enable and Interrupt-disable www.bookspar.com | Website for students | VTU NOTES

  24. Enabling and disabling interrupts • Consider a case of single interrupt request signal from a device.. • When the device activates interrupt-request signal, it keeps it activated until it learns that the processor has accepted its request • This active request signal should not cause successive interruptions, causing the system to enter into infinite loop from which it cannot recover. www.bookspar.com | Website for students | VTU NOTES

  25. 3 mechanisms for stopping infinite loop • The processor hardware ignores the interrupt-request line until execution of the first instruction of the interrupt-service routine has been completed • Usually this first instruction will be interrupt-disable instruction • Last instruction before return-from-interrupt instruction will be interrupt-enable instruction • Processor automatically disables interrupts before starting execution of interrupt-service routine • After saving contents of PC and Processor status(PS) register on the stack, processor performs equivalent of interrupt-disable instruction • One bit in PS-register will be interrupt-enable bit. An interrupt received while this bit is 1 will accept else rejected • When return-from-interrupt instruction is executed, the contents of the PS are restored from the stack, setting Interrupt-enable bit back to 1. • Processor has a special interrupt-request line for which the interrupt-handling circuit responds only to the leading edge of the signal. • Such a line is called edge-triggered www.bookspar.com | Website for students | VTU NOTES

  26. Typical scenario • The device raises an interrupt request • The processor interrupts the program currently being executed • Interrupts are disabled by changing the control bits in the PS ( except in the case of edge triggered interrupts ) • The device is informed that its request has been recognized, and in response, it deactivates the interrupt-request signal • The requested action is performed by interrupt-service routine • Interrupts are enabled and execution of the interrupted program is resumed www.bookspar.com | Website for students | VTU NOTES

  27. Handling multiple devices • A number of devices capable of initiating interrupts are connected to the processor. • Since these devices are operationally independent, there is no particular order in which they generate interrupts • For eg., device X may request an interrupt when an interrupt caused by device Y is being serviced • Also, several devices may request interrupts at exactly the same time www.bookspar.com | Website for students | VTU NOTES

  28. Handling multiple devices • A number of questions to be answered • How can the processor recognize the device requesting interrupt? • Given that different devices are likely to require different-service routines, how can the processor obtain the starting address of the appropriate routine in each case? • Should a device be allowed to interrupt the processor while another interrupt is being serviced? • How should two or more simultaneous interrupt requests be handled? www.bookspar.com | Website for students | VTU NOTES

  29. Handling multiple devices • When a interrupt request is received over the common interrupt-request line, additional information is needed to identify the particular device that activated the line. • If two devices request interrupt at same time, it must be possible to break tie and select one of the two requests for service. • the information whether a device is requesting an interrupt is available in its status register. • The device sets one of the bits in status register called IRQ to 1. • For e.g., bits KIRQ and DIRQ are interrupt request bits for keyboard and display respectively www.bookspar.com | Website for students | VTU NOTES

  30. Handling multiple devices • Simplest way to identify the interrupting device is to poll all the I/O devices connected to the bus • The first device encountered with its IRQ bit set is the device that should be serviced • Polling is easy to implement. Its main disadvantage is time spent in interrogating the IRQ bits of all the devices that may not be requesting any service • An alternative is vectored interrupts www.bookspar.com | Website for students | VTU NOTES

  31. Usage of vectored interrupts • To reduce the time involved in polling process, a device requesting interrupt will identify itself directly to the processor • By sending a special code over the bus, which may represent the starting address of the interrupt-service routine for that device. • The code length is typically between 4-8 bits • Processor can immediately start executing the routine www.bookspar.com | Website for students | VTU NOTES

  32. Usage of vectored interrupts • This arrangement implies that the interrupt-service routine for a given device must always start at the same location. • The programmer can gain flexibility by storing in this location an instruction that causes a branch to the appropriate routine • So in many computers, the location pointed to by the interrupted device is used to store the starting address of the interrupt-service routine • The processor reads this address called as the interrupt vector and loads it into the PC • Interrupt vector may also include a new value for the processor status register www.bookspar.com | Website for students | VTU NOTES

  33. Usage of vectored interrupts • I/O devices in most computers, send the interrupt-vector code over the data bus, using the bus control signals to ensure that devices do not interfere with each other. • When a device sends an interrupt request, processor may not be ready to receive interrupt-vector code • It must first complete the execution of the current instruction, which may require the use of the bus • Further delays caused, if interrupts happen to be disabled at the time request is raised. • Interrupting device waits to put data on the bus only when the processor is ready to receive it. • When the processor is ready, it activates the interrupt-acknowledge line, INTA. • The I/O device responds by sending its interrupt-vector code and turning off the INTR signal www.bookspar.com | Website for students | VTU NOTES

  34. Interrupt nesting • Often when there are several devices involved, execution of a given interrupt-service routine, once started will always continues to completion before the processor accepts an interrupt request from a second device. • The delay caused in accepting the request of another device is acceptable to most simple systems • For some devices, a long delay in responding to an interrupt request may lead to erroneous operation • Eg., a computer that keeps track of time of the day using a real-time clock • To accept an interrupt request during the execution of an interrupt-service routine for another device, I/O devices should be organized in a priority structure. • An interrupt request from a high-priority device should be accepted while the processor is servicing another request from a lower-priority device www.bookspar.com | Website for students | VTU NOTES

  35. Interrupt nesting • A multiple-level priority organization means during execution of an interrupt-service routine, interrupt requests from some devices are accepted but not from others, depending upon the device’s priority. • Assign a priority level to the processor that can be changed under program control • The priority level of the processor is the priority of the program that is currently being executed • The processor accepts interrupts only from those devices that have priorities higher than its own www.bookspar.com | Website for students | VTU NOTES

  36. Interrupt nesting • The processor’s priority is usually encoded in a few bits of the processor status word. It can be changed by program instructions that write into the PS. • These instructions are privileged instructions, which can be executed only while the processor is running in supervisor mode • The processor is in supervisor mode only when executing OS routines • It switches to user mode before beginning to execute application programs • An attempt to execute a privileged instruction while in the user mode causes a special type of interrupt called the privilege exception www.bookspar.com | Website for students | VTU NOTES

  37. Figure 4.7. Implementation of interrupt priority using individual interrupt-request and acknowledge lines. www.bookspar.com | Website for students | VTU NOTES

  38. How to handle simultaneous requests from multiple devices? • The processor must have some means of deciding which request to service first • In prev figure we implemented a priority scheme where different devices have different interrupt request lines • If several devices share a single interrupt request line, we need a different mechanism • One simplest mechanism is polling the devices’ status registers • Priority is determined by the order in which the devices are polled • Only one device should send interrupt vector code www.bookspar.com | Website for students | VTU NOTES

  39. How to assure that only one device sendsinterrupt vector code? • Common mechanism used is daisy chain model • INTR line is common to all devices • INTA is connected in a daisy chain fashion • INTA signal propagates serially through the devices • When several devices raise an interrupt request, and INTR line is activated, the processor responds by setting the INTA line to 1. Device1 passes signal to Device2 only if it does not require any service • So, in daisy chain model, the device that is electrically closest to the system has the highest priority www.bookspar.com | Website for students | VTU NOTES

  40. Simultaneous requests using a combination of both • In interrupt priority scheme using individual INTR and INTA lines, it allows the processor to accept interrupt requests from some devices but not from others, depending upon their priorities. • In daisy chain model, the main advantage is that it requires fewer lines. • A combination of daisy chain and multiple priority scheme is followed in many computers www.bookspar.com | Website for students | VTU NOTES

  41. I N T R Processor Device 1 Device 2 Device n INTA (a) Daisy chain I N T R 1 Processor Device Device INTA1 I N T R p Device Device INTA p Priority arbitration circuit (b) Arrangement of priority groups Figure 4.8. Interrupt priority schemes. www.bookspar.com | Website for students | VTU NOTES

  42. Controlling device requests • Till now we assumed that an I/O device interface generates an interrupt request whenever it is ready for I/O transfer. • For eg., whenever the SIN flag is 1 • We need to take care that only those I/O devices that are being used by a given program generate interrupt request • Idle devices must not be allowed to generate interrupt-requests • Hence need a mechanism in the interface circuits of devices to control whether the device is allowed to generate an interrupt request. • Control is usually provided by interrupt enable bit ( KEN for eg., for Keyboard ) • Then interface circuit of a device generates interrupt request whenever the corresponding status flag ( SIN for keyboard ) is set. • Interface circuit sets bit KIRQ to indicate that the keyboard is requesting an interrupt www.bookspar.com | Website for students | VTU NOTES

  43. D A T AIN D A T A OUT KIRQ SIN ST A TUS KEN CONTR OL 7 6 5 4 3 2 1 0 aces Figure 4.3. Re gisters in k e yboard and display interf SIN – whenever it is 1,Keyboard requests an interrupt KEN – keyboard enable KIRQ – Interrupt Request from Keyboard www.bookspar.com | Website for students | VTU NOTES

  44. Controlling device requests – 2 mechanisms • At the device end, an interrupt-enable bit in a control register determines whether the device is allowed to generate an interrupt request. • At the processor end, either an interrupt enable bit in the PS register or a priority structure determines whether a given interrupt request will be accepted www.bookspar.com | Website for students | VTU NOTES

  45. Exceptions • The term exception is used to refer to any event that causes an interruption. • I/O interrupts are one example of an exception • Some other kinds of exceptions are • Exceptions to recover from errors • Exceptions for debugging • Privilege exception www.bookspar.com | Website for students | VTU NOTES

  46. Exceptions – recovery from errors • For eg., many computers include an error-checking code in the main memory, which allows detection of errors in the stored data. • If an error occurs, the control hardware detects it and informs the processor by raising an interrupt • Processor interrupts a program if it detects an error or an unusual condition while executing instructions • For eg., the OP-code field of an instruction may not corrrespond to any legal instruction, or an arithmetic instruction may attempt a division by zero. • Processor suspends the current program being executed and starts an exception-service routine. • This routine takes appropriate action to recover from error • Or informs the user about it. • The processor most probably may not complete the execution of current instruction and begins exception processing immediately www.bookspar.com | Website for students | VTU NOTES

  47. Exceptions-debugging • Helps programmer to find errors in the program • Debugger software usually provides two important facilities - trace and breakpoint • In trace mode, an exception occurs after execution of every instruction of the debugged program, using the debugging program as the exception-service routine. • The debugging program enables the user to examine the contents of registers, memory locations etc • The trace exception is disabled during the execution of debugging program • Breakpoints provide a similar facility, except that the program being debugged is interrupted only at specific points selected by the user. • An instruction called trap or software interrupt is provided for this purpose • The debugging program saves instruction i+1 and replaces it with a software interrupt instruction • When program execution reaches that point, program is interrupted and debugging routine is activated • When user is ready, debugging routine restores saved instruction and executes a return-from-interrupt instruction www.bookspar.com | Website for students | VTU NOTES

  48. Exceptions-privilege exception • To protect the OS of a system from being corrupted by user programs, certain instructions can be executed only while the processor is in the supervisor mode • These instructions are called privileged instructions • Eg., when a processor is running in the user mode, it will not execute an instruction that changes the priority level of the processor or that enables a user program to access areas in the computer memory that have been allocated to other users. • An attempt to execute such an instruction will produce a privilege exception, • Causes the processor to switch to the supervisor mode • Begin executing an appropriate routine in OS. www.bookspar.com | Website for students | VTU NOTES

  49. Direct memory access - Introduction • In previous sections, Data are transferred by executing instructions such as Move DATAIN, R0 • An instruction to transfer input or output data is executed only after the processor determines that the I/O device is ready. • To do this, the processor either • polls a status flag in the device interface or • waits for the device to send an interrupt request. • In either case, considerable overhead is incurred, because • several program instructions must be executed for each data word transferred. • In addition to polling the status register of the device, instructions are needed for incrementing the memory address and keeping track of the word count. • When interrupts are used, there is the additional overhead associated with saving and restoring the program counter and other state information www.bookspar.com | Website for students | VTU NOTES

  50. Direct Memory access • To transfer large blocks of data at high speed, an alternative approach is used. • A special control unit may be provided to allow transfer of a block of data directly between an external device and the main memory, without continuous intervention by the processor. • This approach is called direct memory access, or DMA. www.bookspar.com | Website for students | VTU NOTES