EKT 221/4 DIGITAL ELECTRONICS II

1. EKT 221/4 DIGITAL ELECTRONICS II • Registers, Micro-operations and Implementations -Part3

2. Outlines • Multiplexer-based transfers • Transforming Block Diagram to Detailed Logic • Shift Registers • Shift Registers with Parallel Loads • Shift Registers with Parallel Loads and Hold • Bidirectional Shift Register • MUX-Based Transfer • Bus-Based Transfer • Serial Transfer and Micro-operations

3. Multiplexer-Based Transfers • A Register receives data transfers from more than 1 sources. • A dedicated multiplexeris used to select the wanted input • Example shows: • R0 receives data from R1 if K1 is 1. • R0 receives data from R2 if K1 is 0. K2 K1 R2 n=4 S R0 0 n=4 1 R1 MUX n=4

4. Multiplexer-Based Transfers • How do we represent this in RTL form? • Written in if-then-else: If (K1=1) then (R0 R1) else if (K2=1) then (R0 R2) • Written in RTL K1:R0 R1, K1K2:R0 R2 K2 K1 R2 n=4 S R0 0 1 n=4 R1 MUX n=4

5. Multiplexer-Based Transfers K1:R0 R1, K1K2:R0 R2 Analyze the diagram for input: K2 K1 R2 n=4 Load S R0 0 1 n=4 R1 MUX n=4

6. K2 K1 Load K2 K1 2 to 1 MUX Load D0 D1 D2 D3 Q0 Q1 Q2 Q3 R2 R2 S Block Diagram n=4 A0 A1 A2 A3 Load S R0 R0 0 Q0 Q1 Q2 Q3 Y0 Y1 Y2 Y3 Load 1 n=4 B0 B1 B2 B3 R1 MUX CLK n=4 Q0 Q1 Q2 Q3 D0 D1 D2 D3 D0 D1 D2 D3 R1 Detailed Logic Transforming a Block Diagram into Detailed Logic

7. Shift Registers • Shift Registers move data laterally within the register toward its MSB or LSB position • In the simplest case, the shift register is simply a set of D flip-flops connected in a row like this:

8. Shift Registers Parallel Output Serial Output Serial Input • Data input, In, is called a serial inputor the shift right input. • Data output, Out, is often called the serial output. • The vector (A, B, C, Out) is called the parallel output.

9. Shift Registers • T0 is the register state just before the first clock pulse occurs • T1 is after the first pulse and before the second. • Initially unknown states are denoted by “?” • Complete the last three rows of the table

10. Shift Registers with Parallel Load • The shift register shown earlier has no control input, thus data is always shifted on clock pulse • How to make the shift registers more controllable?

11. Shift Registers with Parallel Load • By adding a mux between each shift register stage, data can be shifted or loaded • If SHIFT is LOW, A and B are replaced by the data on DA and DB lines, else data shifts right on each clock. 2 to 1 MUX Dn A0 A1 IN Selector SHIFT

12. Shift Registers with Parallel Load • But what if we want to hold to the current data, meaning no shift or no loading of new data? • The design must have 2 controls: • For the SHIFT • For the LOAD We use an AND gate to disabled the Load input, so we mark with don’t care condition

13. In Register Transfer Language: Shift : Q slQ, Shift Load : Q D SHIFT REGISTER WITH PARALLEL LOAD AND HOLD OPERATION

14. Bidirectional Shift Register

15. Bidirectional Shift Register • Unidirectional Register • Capable of shifting only in one direction (like what we have discussed in last lecture) • Shift on clock pulse • Shift & Load • Shift, Load & Hold * shift occurs in one direction only • Bidirectional Register • A register that can shift in both directions • Shift Left (sl) • Shift Right (sr) And at the same time is capable of HOLD and LOAD

16. A1 A2 A3 A4 4 to 1 mux S0 S1 Bidirectional Shift Register • By placing a 4-input multiplexer in front of each D flip-flop in a shift register, we can implement a circuit with shift right, shift left, parallel load, hold.

17. Bidirectional Shift Register How do we represent his in RTL : (No Transfer occurs) S1S0 : Q slQ S1S0 : Q srQ S1S0 : Q D

18. Bidirectional Shift Register • Lets analyze the single stage diagram of a Bidirectional Shift Register

19. Bidirectional Shift Register • Shift registers can also be designed to shift more than a single bit position right or left

20. Bidirectional Shift Register • Shift register can be designed to shift a variable number of bit positions specified by a variable called a shift amount.

21. 4 Bits Bidirectional Shift Register

22. MUX-based Transfer

23. Dedicated MUX – based Transfer • Multiplexer connected to each register input produces a very flexible structure • Characterize the simultaneous transfers possible with this structure

24. Example 1: S0, S1, S2 = (0,0,1) and L0, L1, L2 = (0,0,1) then L2 : R2 ← R1

25. Example 2: S0, S1, S2 = (1,0,0) and L0, L1, L2 = (0,1,1) then L1: R1 ← R0, L2 : R2← R0

26. MUX and Bus – based transfer for Multiple Registers • Multiplexer dedicated to each register • Excessive amount of logic • High number of interconnections • 3 n-bit 2-to-1 MUX • Each with own “Select” signal • Each register has own “Load” signal

27. MUX and Bus – based transfer for Multiple Registers Solution to the problem : • Shared transfer paths for registers • A shared transfer object is called a bus • Bus implementation using : • Multiplexers • Three – state nodes and drivers • In most cases, the number of bits is the length of the receiving register

28. Multiplexer Bus • Only need a single n-bit 3-to-1 MUX and parallel load registers • MUX outputs are shared as common path (bus) • SELECT • Determine contents of source register • LOAD • Determine destination register / register to be loaded with data

29. Multiplexer Bus Example 1: S1, S0 = (0,0) and L0, L1, L2 = (0,0,1) then L2 : R2 R0

30. Example 2: S1, S0 = (1,0) and L0, L1, L2 = (1,1,0) then L0: R0 R2, L1 : R1 R2 Multiplexer Bus

31. Multiplexer Bus Example 3: S1, S0 = (1,0) and L0, L1, L2 = (0,1,1) then L1: R1 R2, L2 : R2 R2 (n.change)

32. Multiplexer Bus • A single bus driven by a MUX lowers cost, but limits the available transfers • Characterize the simultaneous transfers possible with this structure… • Characterize the cost savings compared to dedicated MUX…

33. Multiplexer Bus • 3rd transfer : cannot be done • Requires 2 simultaneous sources in a single bus • Cannot occur in 1 clock cycle • Requires at least 2 buses • However, dedicated MUX can do this

34. MUX-based vs Bus-based • MUX-based • Any combination of transfers is possible • Bus-based • Simultaneous transfers from different sources in single clock cycle is impossible • Reduction in hardware • Limitation in simultaneous transfers

35. Three – state Bus

36. Three – state Bus • The 3 – input MUX can be replaced by a 3 – state node (bus) and 3 – state buffers • Cost is further reduced • Signals can travel in 2 directions • Use same bus to carry signals into and out of registers

37. Serial Transfers & Micro-operations

38. Serial Transfers & Microoperations • Serial transfers • Used for “narrow” transfer paths • Example : Telephone or cable line • Parallel – to – Serial : at source • Serial – to – Parallel : at destination • Serial micro-operations • Example 1 : Addition • Example 2 : Error – Correction for CDs Serial  Parallel Parallel  Serial Source Destination

39. Serial Transfers • Serial mode  info is transferred / manipulated one bit at a time • Serial transfer from RA to RB is done with shift registers

40. Serial Transfers • Serial output (SO) of A connected with serial input (SI) of B • SI of A receives 0’s • Data from A transferred to B • Initial content of B shifted out to SO of B and lost

41. Serial Transfers • To maintain the data in A, connect SO of A to its SI

42. Serial Transfers • Shift determine when & how many times the registers are shifted • Clock pulse (Clock) can pass to C only when Shiftis HIGH (1)

43. Serial Transfers

44. Serial Micro-operations • Serial addition is a low cost way to add large numbers of operands, since a “tree” of full adder cells can be made to any depth. • Other operations can be performed serially as well, such as parity generation / checking or more complex error – check codes. • Shifting a binary number left = multiplying by 2 • E.g:sl 0100  1000 • Shifting a binary number right = dividing by 2 • E.g:sr 0100  0010

45. Serial Adder • The circuit shown uses 2 shift registers for operands • A (3 :0) • B (3:0) • A full adder, and one more FF (for carry) is used to compute the sum • Result stored in A register and final carry in FF

46. Serial Adder • SI of B can receive new inputs • In each clock pulse / cycle : • New sum bit is transferred to A • New carry transferred to FF • Both registers shifted once to the right • Process cont. until Shift = 0

47. Analyzing the circuit : Serial Adder Example 1: Reg A : 1000 Reg B : 0101

48. Analyzing the circuit : Serial Adder Example 2: Reg A : 1011 Reg B : 0101

49. Sin Sin A0 FA S0 B0 B0 A0 Reg B Reg A Cin A1 B1 A2 B2 S1 FA B3 A3 A1 B1 Sout Sout FA S2 A2 B2 FA S3 A3 B3 Cout Parallel Adder Can be the input for Reg A

50. Serial vs. Parallel Transfers • Space vs. Time Trade-off • Serial adder is a sequential circuit because it includes the carry from FF. but need n clock cycle to complete the addition (Less Space, more Time) • Parallel adder is a combinational circuit because it needs n FA for n bit operation. Need only one clock cycle to complete the addition. (More Space, less Time) • Gives the designer choice. • More Space – More cost • More Time – More delay (not fast)