TOT01 ASIC – First Results (STS prototype chip – first results)

1. TOT01 ASIC – First Results(STS prototype chip – first results) Krzysztof Kasiński, Paweł Gryboś , Robert Szczygieł kasinski@agh.edu.pl pawel.grybos@agh.edu.pl robert.szczygiel@agh.edu.pl Department of Measurement and Instrumentation AGH – UST Kraków, PolandCBM Collaboration Meeting, Split, 2009.10.07

2. Agenda Chip overview Test set-up First results Future plans

3. Chip Overview - specification • Specification: • UMC 180 nm technology, (Europractice run 01.06.2009 1.6x3.2mm die) • input charge: 1-16fC (both polarities, much higher charges allowable) • 31 channels (30 regular + 1 test) • Time-over-Threshold (ToT) amplitude measurement method • Low Power (~2.3 mW/channel -> CSA + Discriminator) • Designed for Si Strip Detectors (30pF, 300 um thick, AC-coupled) • Target resolution: 4-6 bits • Noise: ~500 e- (@30pF) To be Verified TOT01 Chip Layout

4. Chip Overview - Architecture Trim DACs 6-bit Back-End: FPGA Gating Counters PC-Interface Etc. Switchable FB Const. Current Discharge Address Threshold Silicon Strip Detector CSA Discriminator Mux • Test Features: • - 3 switchable capacitors at the CSA input • 100fC test pulse injection capacitor • 2 test pulse pads • (voltage step applied to even / odd channels) • Transfer Gate between CSA and Discriminator • Test Pads for probe-station (CSA out, Discr. Out, Discr. 1st stage, DAC out)

5. Chip Overview – Architecture 2 • CSA: • - Folded Cascode • PMOS Input (1.1V) • typ. 500uA current • Source Follower Out • Tuneable Current • Feedback: • - 20 fC Capacitor (metal-metal) • 2 switchable feedback circuits (for both polarities) • Constant Current discharge circuit (typ. 1 – 10nA) • Tuneable discharge current • DAC: • - 6-bit DAC / channel • tuneable offset • tuneable range • Registers + Init Value • Discriminator: • - 2 threshold lines (externally driven) • 1 reference line (Trim DAC driven) • hysteresis • switchable pulse polarity • Mux and output buffer: • - 5-bit Mux routes the channels to the output • Output buffer is separately powered

6. TOT01 Chip Layout 1 - pinout Address, Data, Control Mux out Bias & Switch Decoupling Capacitors Decoupling Capacitors Power supply Power supply Odd channel Test Pulse IN 31 detector interface pads (100um pitch) Even channel Test Pulse IN

7. TOT01 Chip Layout 2 Output buffer Mux 6-bit TrimDACs Address Decoders & Registers Discriminators CSAs Test Pulse Injection caps 3 switchable input caps • Test pads: • CSA output • Discriminator’s first stage outputs • Discriminator output • Trim DAC output * • CSA output after the Transfer-Gate * • * 1st channel only Channel pitch: 50um Die size: 1.6 x 3.2 mm • Empty space will be filled with: • Threshold DACs, • BandGap Reference etc.

8. TOT01 Chip Fabrication and Test progress Design Submission: 01.06.2009 Chip Fabrication: 21.08.2009 EUROPRACTICE MINI@SIC UMC 180 nm Size: 1.6 x 3.2 mm 60 pieces Second Chip bonded -> 02.10.2009 (final PCB set-up) First Chip bonded -> 28.09.2009 (improvised set-up) .

9. Test Set-up Second Chip bonded -> 02.10.2009 (final PCB set-up) Analogue Part Only at the moment First Chip bonded -> 28.09.2009 (improvised set-up) First Check .

10. Final Test Set-Up Functionality Strip Detector Pad (2 x 1.4 cm) HV detector bias (SMA, Filter, Choke, Ileak measurement ) Test Pulse Ports (SMA, 50 ohm, 24:1 divider) Biasing resistors: Icsa , Idischarge Icomp, refb, refa (DAC) Single TOT01 Chip (tantalum, ceramic decoupling) External Control Conn. (DAC & MUX ctrl. + TOT read) Ext. Power Supply Threshold set (DAC, External, Trimmer) • Internal Power Supp. • Analogue: • Low noise 1V VR • Low noise 1.8V VR • Digital: • Regular 1.8 VR • Back-End (FPGA): • 1.2 VR • 2.5 VR • 3.3 VR USB port (PC-link) FPGA (Xilinx Spartan 3, 80Mhz) MEMORY (Fast SRAM 512k x 16)

11. First Power-Up and Biasing Verification • First Check: • Short Circuits Check (O.K.) – no shorts • Power Consumption (O.K.) – no increased power consumption • Bias verification (O.K.) – possible to set the typical bias using expected resistor values • DC voltage levels check (O.K.) – CSA output µ=780mV σ= 20mV • Discriminator operation check (O.K) – varying TH1 and TH2 triggers the discriminator

12. First Transient Plots 1 Variable current Injection through 100fC capacitor • Applied Voltage Step (@ Test Pad): • Min: 4,16 mV ~ 0,42 fC • Max: 416,0 mV ~41,6 fC • Step: 20,8 mV ~ 2,1 fC • Conditions: • Probe placed at CSA output test pad • (large capacitive load: 50cm coax cable + 8pF probe) • Vddm, Vcasc = 1.1 V • Vdd = 1.8 V • Vdd_dig, Vdd_comp = 0 V • Icomp ~ 800uA • Idisch ~ 3nA 5us/div • First Observation of: • - Transient response (O.K. ) – as expected • ToT characteristic (O.K.) – seems linear

13. First Transient Plots 2 Changing Discharge current at the fixed input charge Applied Voltage Step: 208mV ~ 20,8fC Varying the discharge current bias (490K ohm -> 590K ohm) • First Observation of: • Discharge current control (O.K. ) • soon measurements with wider range 5us/div

14. Plans for the future • 1. Run the full-chip set-up • (all biases, external config and measurements) • 2. Functionality verification of all blocks • (esp. Trim DACs) • 3. Further measurements using Test Pulses • (and the switchable input capacitors) • 4. Measurements with the Si Detectors • 5. Run the back-end part (FPGA + memory, USB interface)

15. Summary • TOT01 – Time-over-Threshold based Si Strip detector readout Chip • Submitted: 01.06.2009 • Fabricated: 21.08.2009 • First-Tests: 02.10.2009 Tested: To be Tested: • Power Consumption - Operation with detector • Bias - Trim DAC operation • Discriminator Operation - Noise & resolution • First transients acquired - ToT Linearity

16. Thank you for Your attention ? Questions, suggestions, comments? Krzysztof Kasiński, kasinski@agh.edu.pl Paweł Gryboś, pawel.grybos@agh.edu.pl Robert Szczygieł, robert.szczygiel@agh.edu.pl AGH University of Science and Technology Kraków, Poland