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R/C Simulation and Hardware Proof of Concept Development

R/C Simulation and Hardware Proof of Concept Development. Dr. Philip A. Dafesh, Dr. R. T. Bow, Mr. G. Fan and Mr. M. Partridge Communication Systems Subdivision The Aerospace Corporation. Outline. Background Simulation Overview and Results Hardware Overview and Results

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R/C Simulation and Hardware Proof of Concept Development

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  1. R/C Simulation and Hardware Proof of Concept Development Dr. Philip A. Dafesh, Dr. R. T. Bow, Mr. G. Fan and Mr. M. Partridge Communication Systems Subdivision The Aerospace Corporation

  2. Outline • Background • Simulation Overview and Results • Hardware Overview and Results • Summary and Conclusions

  3. Background • As part of the R/C code Development, Constellation Simulations and Hardware Proof of Concept (POC) Demonstrations Were Completed • Signal Processing Worksystem (SPW) Simulation of L5 and Newly Proposed TDMA Code • HW POC was Developed as a Modification to The Aerospace Corporation's "FlexGPS" FPGA-Based Prototyping System • IIRM Modulator Implementation of C/A, P and M-code on L2 • Single Channel Receiver Hardware (Code Corr. and Tracking Loops) • Implemented R/C Transmitter and Receiver as Modification to C/A Hardware in 2 Weeks from Receipt of the R/C Specification • Simulated and Measured Correlation Response and DLL Tracking Loop Response for R/C Codes Alternatives

  4. Sample Correlation Data Taken with R/C Code POC Hardware Measured Correlation is In Agreement With Theoretical Reduction in Non-Prompt Correlation for a Single Satellite

  5. Simulation • Implements Multiple R/C Code Satellites Using the Signal Processing WorkSystem (SPW) • Simulates the Effect of Random Code Phases and Carrier Doppler for Each Satellite • 10 Satellites in View at Varying Power Levels • Signal Parameters are Adjusted to Mimic the IIRM Implementation • Interplex Modulation of C/A or TDMA, P(Y) and M-Code • Relative Power Adjusted to IIRM Levels

  6. Caveats • M-Code Implemented as a 20 TAP M-Sequence • Actual Code is Nonrepeating • Used Actual P-Code • Used Actual C/A and TDMA Codes • Simulation Sample Rate = 4.092x107 • 40 Samples/TDMA Chip (80 Samples/Bit) 1 Bit ~ 2 s 1Chip~ 1 s M0L0M1L1M2L2M3L3M4L4

  7. Normalized Correlation of SV1 with Constellation (with P and M)

  8. Zoom in to TDMA/CA Results

  9. Summary of Observations • R/C Code Correlation Results in Fewer and Smaller Size Non-Prompt Code-Cross Correlations with other Satellites than Does C/A Code • Results Indicate that R/C Code Should Result in Smaller CDMA Noise Contributions During Tracking and Fewer False Alarms During Acquisition • Even when Constellation of Satellites is Considered Including Effects of Doppler, Amplitude and Phase Distribution

  10. Hardware Proof of Concept Description • Implementation of a Single IIRM Satellite with Switches to Select Different R/C Code Options on the L2 Carrier • C/A, L5, TDMA • Receiver Can Select Between Correlation of Entire TDMA or Individual 2CM and 2CL Codes • Selectable DLL Early-Late Code Tracking at Spacing from +/- 0.05 chips to +/- 0.5 chips • SVi to SVi Autocorrelation and SVi to SVk Cross-Correlation • New TDMA Code was Implemented in FlexGPS Transmitter and Receiver Correlator within 2 Weeks • Relatively Straightforward Modification to C/A Receiver

  11. Hardware Description (Cont.) • All Tests Conducted at L2 Frequency • Correlation Sweep and DLL Tracking at Selectable Early-Late Spacing, Loop Parameters • No Navigation Processing • I and Q Sample Rate = 40.92 MHz • Receiver Bandwidth = 24 MHz • Data Measurement and Diagnostic Capability • Time-Domain, Frequency-Domain & Logic-Level • Oscilloscope, Spectrum Analyzer, Logic Analyzer • PR Residual and Code Correlation Data • Software GUI Control and Data Acquisition Interface

  12. Aerospace’s FlexGPS Prototyping System

  13. Rapid-Prototype BoardClose-Up of Modulator and Receiver Tx I/Q DACs Rx 40.92 MHz I/Q ADCs

  14. Tx/Rx Signal Probe and Control Logic Analyzer Probes GUI Interface Control and I/O

  15. What's Different from Prior C/A-Code Prototype • What was Implemented • SV Selectable C/A, L5 or TDMA Code at Transmitter • Selectable 2CM, 2CL, L5-I or C/A Codes in Receiver • 511.5 kHz Square-Wave Gated Integrate and Dump Clock ("0" of square-wave corresponds to 2CM Accumulator Clock and "1" Corresponds to 2CL Accumulator Clock) • Square-wave Gated Correlator With Standard Bi-Phase (+1,- 1) Reference Used Instead of Three-Level (+1,0,-1) Reference Code • No Significant Changes to C/A Code DLL Tracking Channel • Additional Details to be Published at ION GPS 2001 • What was Not Implemented (Planned) • Independent 2CM and 2CL Tracking Channels • Viterbi decoding

  16. R/C TDMA Specific Additions • Difference Between C/A and TDMA Receiver Hardware • Requires 2 Code Generators • Same Hardware Initialized Differently and Short Cycled at Different Points to Generate 2CM and 2CL Codes • Requires Different Correlation Method • Implemented as Time Gating or 3-Level Reference • Requires Min of 1 and Max of Two New Tracking Channels for L2 Reception • Additional Changes Include Standard Viterbi Decoding and Carrier PLL Carrier Tracking as would be Implemented for the L5 Signal • Associated Data Demodulation at 25 Hz Rate (50 Hz Coded)

  17. Hardware Measured Power Spectral Density TDMA Signal PSD Follows Same Sinc2 Response as C/A Without Observable Spectral Lines

  18. Measured Spectral Lines Line Structure of TDMA R/C Code is Within Resolution of Spectrum Analyzer < 1 Hz Line Spacing TDMA R/C Code Has P-Code Like Line Structure: Better Interference Rejection Properties

  19. Measured R/C vs C/A Correlation and Pseudorange Measured Mean PR Residual of 803 PR I&D Samples (in Chips):

  20. Summary of Hardware Measurement Observations • TDMA Code Has an Undetectable Spectral Line Structure • More P-Code Like and Potentially Better Immunity to Co-Channel Interference than C/A or L5 • TDMA Correlation Response • Comparable to C/A Code but 1/2 the Magnitude for Correlation Over Fixed Integration Period • In agreement with Theoretically Expected Multiplexing Ratio • Significantly Smaller Amplitude Non-Prompt Peaks • Better Acquisition Performance, Smaller CDMA Noise • TDMA Code Pseudorange Response Does Not Exhibit any Biases Relative to C/A Code • Agreement to 0.0001 C/A Chip (within Experimental Error)

  21. Planed Hardware Additions • Implementation of Code and Carrier Tracking for Various Combinations • Code and Carrier Tracking 2CM Code with Data • Early-Late Code Tracking, AFC and PLL Carrier Tracking with Data removal • Code and Carrier Tracking 2CL Code without Data • Early-Late Code Tracking, AFC and PLL Carrier Tracking without Data removal • Acquisition Performance of C/A vs 2CM vs 2CL • Industry Inputs Welcome • To Address Specific Concerns with TDMA Receivers

  22. Summary and Conclusions • C/A, L5 (1.023 MCPS) and TDMA Code R/C Options were Compared Using a Constellation Simulation and a FPGA Hardware Proof of Concept • New L2 TDMA R/C Code Exhibited Superior Characteristics • A Proof of Concept was Developed for Both Transmitter and Receiver Implementations of the L2 R/C Code • Small Change to Aerospace's FlexGPS Receiver Implemented by Time Gated Correlator with 511.5 kHz Square-wave • Simulation and Hardware Measurements are Constant with Theoretical Expectations for TDMA R/C Codes • Detailed Results to be Published at ION GPS 2001

  23. Backup

  24. Current Prototype Development Approach SPW/C Floating Point Simulation HDS (Fixed Pt. SPW ) Model Development Integrated SPW w/ Hardware Development System (HDS) Simulation: Cycle Correct Fixed Point (Integer) Simulation Concept to Hardware HDS Subsystem Optimization (Digital Design) HDS: Optimized Prototype Design VHDL Code Generation Sun Workstation Synthesize VHDL to EDIF/XNF Compile FPGA File LAN APTIX Software: Place and Route FPGA Components, Interconnect Routing, Test Points Selection FPGA APTIX Programmable Brassboard HP Logic Analyzer

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