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Verification & Test Activities @ CISS – Aalborg. Brian Nielsen Kim Guldstrand Larsen Arne Skou. Overview. CISS Verification & Scheduling S/E-machines, UML & visualSTATE Timed Automata & UPPAAL Priced Timed Automata & UPPAAL CORA Markov Decision Processes & RAPTURE Testing

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overview
Overview
  • CISS
  • Verification & Scheduling
    • S/E-machines, UML & visualSTATE
    • Timed Automata & UPPAAL
    • Priced Timed Automata & UPPAAL CORA
    • Markov Decision Processes & RAPTURE
  • Testing
    • Connectivety Testing
    • On-line Testing & UPPAALTRON
    • GateHouse, Generic Test Adaptation
    • visualSTATE Test Extensions
ciss center for embedded software systems 2002
CISS Center for Embedded Software Systems, 2002 –

MVTU

25.5 MDKK

Regional & City

Councils

12 MDKK

External collaboration:

EE&CS Berkeley

Twente U

Uppsala U

AMETIST

ARTIST

NASA Ames

ICT Companies

Aalb. Uni

12.75 MDKK

Companies

12.75 MDKK

Institute for

Computer Scienc

Institute for

Elektronic Systemer

BRICS@Aalborg

Modelling and Validation;

Programming Languages;

Software Engineering

Distributed

Real Time Systems

Control Theory;

Real Time Systems;

Networking.

Embedded Systems

Communication;

HW/SW

Power Management

20 Staff / 12 PhD studens

focus areas
Focus Areas

Applikationer

Model Based Development of Embedded Software

Home automation

Mobile robotter

Intelligente sensorer

Ad hoc netværk

Mobiltlf

Audio/Video

Konsum elektr

Kontrolsystemer

Automobile

X-by wire

Intelligent Sensor Networks

Embedded & RT Platform LAB

Kommunikationsteori

Resource Optimal Scheduling

Hybride systemer

Test & Validering

Effektforbrug

Pålidelighed

SW-udvikling

Algoritmik

Modeller

Metoder

Safety Critical Software Systems

Protokoller

Design- og Prog.sprog

Operativ system

HW platform

GPS

Open source

Embedded System Testing & Verification

Teknologi

Værktøj

HW/SW Co-Design, Design Space Exploration

visualstate
visualSTATE
  • UML compatible development tool
  • Automatic code-generation
  • Check for generic properties.
  • Patented CBR technique developed in 1998 [TACAS98, TACAS99]
  • New project:
    • Extension of visualSTATE w test-case generation facilities
    • Context dependent code-generation [FASE05]
    • Improvement of verification engine (handling of signal-queue).
modus operandi
Modus Operandi

Theoretical development & validation

IDEA

e.g.

language extension

datastructure

abstraction

algorithm

Prototype implementation

&

performance evaluation

In-house evaluataion

Incorporation in official release

issues
Datastructures for Passed and Waiting

Datastructures for zones

Do we really need to always store in Passed ?

Do we really need to add all successors ?

Which symbolic state to select from Waiting ?

Issues
passed waiting
Passed/Waiting

[SPIN03]

States

Hash

table

PASSED

Hash

table

WAITING

passed waiting1
Passed/Waiting

[SPIN03]

States

Hash

table

States

UNIFIED

Hash

table

PASSED

Hash

table

Waiting queue

WAITING

passed waiting2
Passed/Waiting

[SPIN03]

States

Hash

table

States

UNIFIED

Hash

table

PASSED

Hash

table

Waiting queue

to store or not
To-store-or-not

117 statestotal

!

81 statesentrypoint

!

9 states

[CAV03]

datastructures for zones
Datastructures for Zones

-4

  • DBMs
  • Minimal Constraint Form
  • CDDs

x1

x2

4

3

3

2

-2

-2

2

x0

x3

1

5

UPPAAL library to be made available

Alexandre David

zone abstractions
Zone Abstractions

[TACAS03,TACAS04]

  • Abstraction taking maximum constant into account necessary for termination
  • Utilization of distinction between lower and upper bounds
  • Utilization of location-dependency
lu abstraction
LU Abstraction

[TACAS04]

THEOREM

For any state in the LU- abstraction there is a state

in the original set simulating it

LU abstraction is exact wrt reachability

zone abstractions1
Zone abstractions

Classical

Loc. dep. Max

Loc. dep. LU

Convex Hull

symmetry reduction
Symmetry Reduction

[Formats 2003]

  • Exploitation of full symmetry may give factorial reduction
  • Many timed systems are inherently symmetric
  • Computation of canonical state representative using swaps.
symmetry reduction1
Symmetry Reduction

[Formats 2003]

analysis methods identified
Analysis Methods Identified
  • Techniques identified and implemented:
    • Zone abstractions (max constant, loc.dep., lower/upper bounds)
    • Storage techniques
    • Symmetry reduction
    • Cost-guiding search and pruning
    • Distributed exploration
    • Cycle acceleration
    • Sweep line reduction
  • Conclusion: “ Progress by far exceeding expectations ”
  • Future: “ Consolitation & combination ”
uppaal cora1

x ¸ 4

x ¸ 5

x:=0

c+=1

C

c’=1

c’=5

x · 2

y:=0

y=0

G

A

B

c´=10

c+=7

x:=0

x ¸ 4

C

x ¸ 3

UPPAAL CORA

Priced Timed Automata

  • Branch of UPPAAL with support for cost-optimal reachability.
  • Based on priced zones
  • Substantial performance improvement by translation to min-cost-flow problems
  • Competitive with MILP
  • Possibility of guiding (improving) search by heur and remaining meta-variable.
  • Fully compatible w UPPAAL (GUI).
  • Application to AXXOM case-study.
  • Application to vehicle routing problems w time-windows (Carmen Consulting).
  • Applied to Dynamic Voltage Scheduling, WCET analysis.
  • Visualization of generated optimal schedules using Gantt charts (to be finished during beginning of 2005).
  • New optimization problems to be added:
    • Optimal Infinite schedules [HSCC’04]
    • Conditional Optimal Schedules [FOSSACS’05]

[HSCC’01, CAV’01, EMSOFT’03, TACAS’04]

s = (A x=y=0)

!0 (B x=y=0)

!0 (C x=y=0)!5,5 (C x=y=5) !1 G

aircraft landing

cost

E earliest landing time

T target time

L latest time

ecost rate for being early

l cost rate for being late

dfixed cost for being late

d+l*(t-T)

e*(T-t)

t

E

T

L

Aircraft Landing

Planes have to keep separation distance to avoid turbulences caused by preceding planes

Runway

uppaal cora2
UPPAAL CORA

Source: Baesley et al’2000

PTA versus MILP on Aircraft Landing Benchmark

DEC300/700 (225MHz) vs Pentium MMX (200 MHz)

slide24
RAPTUREProbabilistic Reachability for Markov Decision ProcessesPedro D’Argenio, Henrik Jensen, Bertrand Jeannet , Kim Larsen

PAPM’01, PAPM’02

process A

{

var x : uint(4);

t : uint(10);

init #send and x=0 and t=0;

loc send:

when x>=4 goto { success 0.01 ; wait 0.99 };

when x<5 and t<200 goto send assign {x:=x+1; t:=t+1};

loc wait:

when x=8 goto send assign {x:=0};

when x<8 and t<200 goto wait assign {x:=x+1; t:=t+1};

loc success:

when true goto success;

}

system A;

initial #A.send and A.x=0 and A.t=0;

final #A.success and A.t<200;

x:=x+1

send

x:=0

x5

x4

x=8

x:=x+1

x8

success

wait

partition refinement
Partition/Refinement

T

0.5

1

0.5

1

0.5

0.4

1

0.6

0.5

0.5

1

1

0.5

0.5

0.5

partition refinement1
Partition/Refinement

T

Ta

0.5

0.5

1

1

1

0.5

0.5

1

0.5

0.4

1

0.6

0.5

0.5

1

1

1

0.5

0.5

0.5

0.5

0.5

1

Theorem

0.5

0.5