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Future Digital Parking Meter: Schematic Review and Implementation Insights

This presentation discusses the development of a cutting-edge digital parking meter. Key aspects include project selection, Java implementation, and modifications in Verilog. It outlines the design process, focusing on the encryption block which handles ticketing and time management for parked cars. Critical components like SRAM and a 7-segment display are detailed, showcasing simulation results and layout considerations. The team has explored various design decisions, emphasizing efficiency and power management as they finalize the project's schematic and layout.

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Future Digital Parking Meter: Schematic Review and Implementation Insights

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  1. Team M1: Anna Kochalko Chris Moody Hong Tuck Liew John Wu Project Manager: Kartik Murthy Parking PalPresentation #6 Your digital parking meter of the future! October 10, 2007 Schematic Review!

  2. Status • Project Chosen • Options explored and eliminated • Wrote Java Implementation • Specification defined • Verilog obtained/modified • Test Benches • Schematic Design • Layout* • Simulations

  3. Encryption Block • Parts in Encryption Block: • 2x 16 bits register • 16 bits Mux • 32 bits Mux • FSM(encryption) • Encryptor (Small Encryption Block)

  4. FSM Encryption

  5. FSM Encryption (Wave)

  6. Encryption Cell

  7. Encryption Cell (Wave)

  8. Full Encryption Block

  9. Full Encryption Wave

  10. Tickets Block • This block is responsible for determining how much time a car has left to park, and whether or not a car should be ticketed. • Major Components: • 11-Bit Adder, 11-Bit Subtractor, 11-Bit Comparator.

  11. SRAM • Included in the following slides are simulation results for an SRAM cell and mult-adder block. • Design decision made: • Not pre-charging for reading because it makes it faster not more power efficient

  12. SRAM Cell

  13. SRAM Cell Wave

  14. SRAM FSM

  15. SRAM FSM WAVE

  16. Overall SRAM

  17. Full SRAM Wave

  18. 7-Segment Display • Included in the following slides are simulation results for a 7-Segment Display block

  19. Binary to BCD (4 bits)

  20. Parallel to Serial

  21. 7-Seg Display Cell

  22. Full 7-Seg Display Block

  23. Full 7-Seg Display(Wave)

  24. Overall Design Schematic

  25. Layout*

  26. Things to Do • Power FSM • Layout • More Layout

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