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AMD Opteron: Multi-core Technology

AMD Opteron: Multi-core Technology. Brittany Smith 24 April 2008. Opteron Quad-core. Released 10 Sept 2007 L3 Cache Problem discovered Dec 2007 Made widely available 9 April 2008 Code named ‘Barcelona’ Four core efficiencies: System CPU Power Virtualization.

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AMD Opteron: Multi-core Technology

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  1. AMD Opteron: Multi-core Technology Brittany Smith 24 April 2008

  2. Opteron Quad-core • Released 10 Sept 2007 • L3 Cache Problem discovered Dec 2007 • Made widely available 9 April 2008 • Code named ‘Barcelona’ • Four core efficiencies: • System • CPU • Power • Virtualization A pair of Opteron 2350 processors

  3. A summary of Barcelona

  4. Processor Architectural Features • Direct Connect Architecture • AMD CoolCore Technology • AMD-V with Rapid Virtualization Indexing • Integrated DDR2 DRAM Controller • AMD Balanced Smart Cache • AMD Wide Floating Point Accelerator

  5. IPC Enhancements • 32B instruction fetch • Enhanced branch prediction • Out-of-order load execution • Up to 4 DP FLOPS/cycle • Dual 128-bit SSE dataflow • Dual 128-bit loads per cycle • Bit manipulation extensions • SSE extensions

  6. Instruction Fetching • Each cycle, Barcelona fetches 32B of instructions from the L1 cache into the predecode/pick buffer • Uses a branch selector to choose between using a bi-modal predictor and a global predictor

  7. Out-of-order Engine • 72 entry reorder buffer • It contains 24 entries, with 3 lanes for instructions in each entry.

  8. Memory System • Barcelona offers non-speculative memory access re-ordering, which means that some memory operations can issue out-of-order. • Each core has 8 data prefetchers, which fill to the L1D cache. The instruction prefetcher for Barcelona can have up to 2 outstanding fetches to any address.

  9. Cache System • L1D cache: 2-way associative, with 64 byte lines and a 3 cycle access time. It uses a write-back policy to the L2 cache, which is exclusive of the L1. • L2 cache: 64B line size and 16-way associative; 4 cycle access time • L3 cache: 32-way associative with 64B lines; undisclosed latency

  10. Barcelona Die Micrograph

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