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Logic Design Review – 3 Basic Sequential Circuits. Lecture L14.3 Verilog. Basic Sequential Circuits. Latches Flip-Flops Registers Counters Shift Registers Datapaths State Machines. R-S Latch. R. Q. S. R-S Latch.

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basic sequential circuits
Basic Sequential Circuits
  • Latches
  • Flip-Flops
  • Registers
  • Counters
  • Shift Registers
  • Datapaths
  • State Machines
r s latch

R-S Latch

R

Q

S

R-S Latch

Q is set to 1 when S is asserted, and remains unchanged when S is disasserted.

Q is reset to 0 when R is asserted, and remains unchanged when R is disasserted.

Assertions can be active HIGH or active LOW

slide4

R-S Latch

R

Q

S

module RSlatch ( Q ,R ,S );

input R ;

wire R ;

input S ;

wire S ;

output Q ;

reg Q ;

always @(R or S)

begin

if(S == 1 && R == 0)

Q = 1;

elseif(S == 0 && R == 1)

Q = 0;

end

endmodule

Active HIGH

slide6

R-S Latch

R

Q

S

module RSlatch ( Q ,R ,S );

input R ;

wire R ;

input S ;

wire S ;

output Q ;

reg Q ;

always @(R or S)

begin

if(S == 0 && R == 1)

Q = 1;

elseif(S == 1 && R == 0)

Q = 0;

end

endmodule

Active LOW

slide8

Note that this is different from the "textbook" RS latch

module RSlatchNOR ( Q ,R ,S );

input R ;

wire R ;

input S ;

wire S ;

output Q ;

wire Q ;

wire F1, F2;

nor #10 (F1,F2,R);

nor #10 (F2,F1,S);

assign Q = F1;

endmodule

10ns propagation delay

slide9

R S Q

0 0 Q0 store

0 1 1 set

1 0 0 reset

1 1 0 disallowed

how can you make this r s latch from gates

R-S Latch

R

Q

S

How can you make this R-S latch from gates?

Q is set to 1 when S is asserted, and remains unchanged when S is disasserted.

Q is reset to 0 when R is asserted, and remains unchanged when R is disasserted.

Assertions can be active HIGH or active LOW

slide11

SQ

R-S Latch

00

01

11

10

R

R

Q

0

S

1

Q is set to 1 when S is asserted (1), and remains unchanged when S is disasserted (0).

Q is reset to 0 when R is asserted (1), and remains unchanged when R is disasserted (0).

R S Q Q

0 0 0 0

0 0 1 1

0 1 0 1

0 1 1 1

1 0 0 0

1 0 1 0

1 1 0 0

1 1 1 1

store

1

1

1

set

1

reset

store

Q = ~R & Q

| ~R & S

| S & Q

slide12

R-S Latch

R

Q

S

RS Latch

R S Q Q

0 0 0 0

0 0 1 1

0 1 0 1

0 1 1 1

1 0 0 0

1 0 1 0

1 1 0 0

1 1 1 1

store

set

reset

store

Q = ~R & Q

| ~R & S

| S & Q

slide13

module RSlatchGates ( Q ,R ,S );

input R ;

wire R ;

input S ;

wire S ;

output Q ;

wire Q ;

assign #10 Q = ~R & Q | ~R & S | S & Q;

endmodule

d latch

D Latch

D

Q

EN

D Latch

Q follows D when EN is high, and remains unchanged when EN is low..

slide16

D Latch

D

Q

EN

module Dlatch ( Q ,EN ,D );

input EN ;

wire EN ;

input D ;

wire D ;

output Q ;

reg Q ;

always @(D or EN)

if(EN == 1)

Q = D;

endmodule

basic sequential circuits1
Basic Sequential Circuits
  • Latches
  • Flip-Flops
  • Registers
  • Counters
  • Shift Registers
  • Datapaths
  • State Machines
d flip flop

Q

D

clk

!Q

D clk Q !Q

0 0 1

1 1 0

X 0 Q0 !Q0

D Flip-Flop

Positive edge triggered

D gets latched to Q on the rising edge of the clock.

Behavior

always @(posedge clk)

Q <= D;

slide20

Q

D

clk

!Q

DFF.v

module DFF (D, clk, Q, notQ );

input clk ;

wire clk ;

input D ;

wire D ;

output Q ;

reg Q ;

output notQ ;

wire notQ ;

always @(posedge clk)

Q <= D;

assign notQ = ~Q;

endmodule

Note non-blocking assignment

slide22

DFFclr.v

module DFFclr (D, clk, clr, Q, notQ );

input clk ;

wire clk ;

input clr ;

wire clr ;

input D ;

wire D ;

output Q ;

reg Q ;

output notQ ;

wire notQ ;

always @(posedge clk orposedge clr)

if(clr == 1)

Q <= 0;

else

Q <= D;

assign notQ = ~Q;

endmodule

Asynchronous clear

basic sequential circuits2
Basic Sequential Circuits
  • Latches
  • Flip-Flops
  • Registers
  • Counters
  • Shift Registers
  • Datapaths
  • State Machines
a 1 bit register
A 1-Bit Register

Behavior

always @(posedge clk)

if(LOAD == 1)

Q0 <= INP0;

slide27

A Generic Register

// An n-bit register with asynchronous clear and load

module register(clk,clr,load,d,q);

parameter n = 8;

input [n-1:0] d;

input clk,clr,load;

output [n-1:0] q;

reg [n-1:0] q;

always @(posedge clk orposedge clr)

if(clr == 1)

q <= 0;

elseif(load)

q <= d;

endmodule

basic sequential circuits3
Basic Sequential Circuits
  • Latches
  • Flip-Flops
  • Registers
  • Counters
  • Shift Registers
  • Datapaths
  • State Machines
slide30

count3

clr

Q(2 downto 0)

clk

3-Bit Counter

Behavior

always @(posedge clk orposedge clr)

begin

if(clr == 1)

Q <= 0;

else

Q <= Q + 1;

end

slide31

counter3.v

module counter3 (clk, clr, Q );

input clr ;

wire clr ;

input clk ;

wire clk ;

output [2:0] Q ;

reg [2:0] Q ;

// 3-bit counter

always @(posedge clk orposedge clr)

begin

if(clr == 1)

Q <= 0;

else

Q <= Q + 1;

end

endmodule

Asynchronous clear

Output count increments

on rising edge of clk

slide33

Clock

4.0 MHz

Q0

2.0 MHz

Q1

1.0 MHz

Q2

0.5 MHz

Q3

0.25 MHz

Clock Divider

Clk4 = 4 MHz clock

basic sequential circuits4
Basic Sequential Circuits
  • Latches
  • Flip-Flops
  • Registers
  • Counters
  • Shift Registers
  • Datapaths
  • State Machines
slide36

shift4.v

module ShiftReg(clk,clr,data_in,Q);

input clk;

input clr;

input data_in;

output [3:0] Q;

reg [3:0] Q;

// 4-bit Shift Register

always @(posedge clk orposedge clr)

begin

if(clr == 1)

Q <= 0;

else

begin

Q[3] <= data_in;

Q[2:0] <= Q[3:1];

end

end

endmodule

Note non-blocking assignment

slide39

ring4.v

module ring4(clk,clr,Q);

input clk;

input clr;

output [3:0] Q;

reg [3:0] Q;

// 4-bit Ring Counter

always @(posedge clk orposedge clr)

begin

if(clr == 1)

Q <= 1;

else

begin

Q[3] <= Q[0];

Q[2:0] <= Q[3:1];

end

end

endmodule

slide42

johnson4.v

module johnson4(clk,clr,Q);

input clk;

input clr;

output [3:0] Q;

reg [3:0] Q;

// 4-bit Johnson Counter

always @(posedge clk orposedge clr)

begin

if(clr == 1)

Q <= 0;

else

begin

Q[3] <= ~Q[0];

Q[2:0] <= Q[3:1];

end

end

endmodule

slide45

Q3 Q2 Q1 Q0

0 0 0 1 1

1 0 0 0 8

1 1 0 0 C

1 1 1 0 E

1 1 1 1 F

0 1 1 1 7

1 0 1 1 B

0 1 0 1 5

Q3 Q2 Q1 Q0

1 0 1 0 A

1 1 0 1 D

0 1 1 0 6

0 0 1 1 3

1 0 0 1 9

0 1 0 0 4

0 0 1 0 2

0 0 0 1 1

slide46

rand4.v

module rand4(clk,clr,Q);

input clk;

input clr;

output [3:0] Q;

reg [3:0] Q;

// 4-bit Random number generator

always @(posedge clk orposedge clr)

begin

if(clr == 1)

Q <= 1;

else

begin

Q[3] <= Q[3] ^ Q[0];

Q[2:0] <= Q[3:1];

end

end

endmodule

slide48

outp

inp

Q2

Q1

Q0

clk

Clock Pulse

slide49

clk_pulse.v

module clk_pulse(clk,clr,inp,outp);

input clk;

input clr;

input inp;

output outp;

wire outp;

reg [2:0] Q;

// clock pulse generator

always @(posedge clk orposedge clr)

begin

if(clr == 1)

Q <= 0;

else

begin

Q[2] <= inp;

Q[1:0] <= Q[2:1];

end

end

assign outp = Q[2] & Q[1] & ~Q[0];

endmodule

slide50

outp

inp

Q2

Q1

Q0

clk

basic sequential circuits5
Basic Sequential Circuits
  • Latches
  • Flip-Flops
  • Registers
  • Counters
  • Shift Registers
  • Datapaths
  • State Machines
slide52

Lab 8

unsigned long sqrt(unsigned long a){ unsigned long square = 1;

unsigned long delta = 3;

while(square <= a){

square += delta;

delta += 2;

}

return (delta/2 - 1);}

basic sequential circuits6
Basic Sequential Circuits
  • Latches
  • Flip-Flops
  • Registers
  • Counters
  • Shift Registers
  • Datapaths
  • State Machines
slide60

// Square root control

module SQRTctrl(Clk, Clear, lteflg, strt, ald, sqld, dld, outld);

input Clk, Clear, lteflg, strt;

output ald, sqld, dld, outld;

reg ald, sqld, dld, outld;

reg[1:0] present_state, next_state;

parameter start = 2'b00, test = 2'b01,

update = 2'b10, done = 2'b11;

// State register

always @(posedge Clk orposedge Clear)

begin

if (Clear == 1)

present_state <= start;

else

present_state <= next_state;

end

slide62

// C1: next state

always @(present_state or start or lteflg)

begin

case(present_state)

strt: if(strt == 1)

next_state <= test;

else next_state <=start;

test: if(lteflg == 1)

next_state <= update;

else next_state <= done;

update: next_state <= test;

done: next_state <= done;

default next_state <= start;

endcase

end

slide64

// C2: outputs

always @(present_state)

begin

case(present_state)

strt: begin

ald = 1; sqld = 0; dld = 0; outld = 0;

end

test: begin

ald = 0; sqld = 0; dld = 0; outld = 0;

end

update: begin

ald = 0; sqld = 1; dld = 1; outld = 0;

end

done: begin

ald = 0; sqld = 0; dld = 0; outld = 1;

end

default begin

ald = 0; sqld = 0; dld = 0; outld = 0;

end

endcase

end

endmodule