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Apurv Kumar Yadav Research Supervisor: Prof. K . Gopakumar

Investigations on Multilevel Voltage Space Vectors Generated by Stacked and Cascaded B asic I nverter C ells with Capacitor Voltage Control for Induction Motor Drives. Apurv Kumar Yadav Research Supervisor: Prof. K . Gopakumar Department of Electronic Systems Engineering

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Apurv Kumar Yadav Research Supervisor: Prof. K . Gopakumar

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  1. Investigations on Multilevel Voltage Space Vectors Generated by Stacked and Cascaded Basic Inverter Cells with Capacitor Voltage Control for Induction Motor Drives Apurv Kumar Yadav Research Supervisor: Prof. K . Gopakumar Department of Electronic Systems Engineering Indian Institute of Science Bangalore, India.

  2. Overview of presentation DESE, Indian Institute of Science, Bangalore, India Introduction Instantaneous balancing of Neutral Point Voltages of stacked DC-link Capacitors A new 7-level hybrid topology Generation of denser 12-sided polygonal voltage space structure Future scope Publications

  3. Adjustable speed AC drive system Fig: Schematics for variable frequency drive Important modules of an adjustable speed AC drive system are, • Rectifier • Three phase Inverter • AC motor DESE, Indian Institute of Science, Bangalore, India

  4. 3-Phase Conventional 2-level Inverter Inverter waveforms Fig: 2-level inverter and space vector structure • 8 (23) switching states possible • Only 2 voltage levels in the pole voltage waveforms • Hence called as two level inverter DESE, Indian Institute of Science, Bangalore, India • VAo is defined as inverter pole voltage. • VAn is defined as motor phase voltage.

  5. Multilevel inverters and their features [1] P.Roshan Kumar, S. Kaarthik, K. Gopakumar, J. Leon, and L. Franquelo, “Seventeen-level inverter formed by cascading flying capacitor and floating capacitor h-bridges,” IEEE Trans. Power Electron., vol. 30, no. 7, pp. 3471–3478, July 2015. DESE, Indian Institute of Science, Bangalore, India Multilevel inverters have more number of levels in the pole voltages, which has following advantages • Improved voltage and current THD. • Reduced dv/dt voltage stress on the switches. • Reduced EMI issues. • Reduced filtering requirements. Commonly used multilevel inverter topologies are • Diode clamped inverter • Flying capacitor inverter (FC) • Cascaded H-bridge inverter (CHB) • Hybrid multilevel inverter [1]

  6. Multilevel Inverters (MLI) Fig: 3-level flying capacitor(FC) Fig: 5-level cascaded H-bridge (CHB) • The NPC suffers from problem of neutral point voltage deviation, in case of single DC-link operation • FC uses more number of floating capacitors. • CHB requires multiple isolated DC power supplies DESE, Indian Institute of Science, Bangalore, India Fig: 3-level neutral point clamped (NPC)

  7. Multilevel Inverters (MLI) Contd.. Fig: 3-level T-type MLI Fig: 5-level Hybrid MLI[1] [1] P. Roshankumar, P. P. Rajeevan, K. Mathew, K. Gopakumar, J. I. Leon, and L. G. Franquelo, “A five-level inverter topology with single-dc supply by cascading a flying capacitor inverter and an h-bridge,” IEEE Transactions on Power Electronics, vol. 27, no. 8, pp. 3505–3512, Aug 2012. DESE, Indian Institute of Science, Bangalore, India

  8. Stacked Inverter Topology • Stacking of basic FC inverter. • Reduced Voltage stress on the devices. • Neutral point balancing of DC link capacitor is obtained, if 6-phase machine is used[2]. [1] R.VijuNair, ArunRahul.S, R.S. Kaarthik, A.kshirsagar, K. Gopakumar, “Generation of Higher Number of Voltage Levels by Stacking Inverters of Lower Multilevel Structures with Low Voltage Devices for Drives,” IEEE Trans.Power Electron., vol. 32, no. 1, pp. 52–59, Jan 2017. [2] R.Viju Nair, ArunRahul.S, SumitPramanick, K. Gopakumar,, and L. Franquelo, “Novel Symmetric Six-phase Induction Motor Drive Using Stacked Multilevel Inverters With a Single DC Link and Neutral Point Balancing,” IEEE Trans.Industrial Electronics., vol. 64, no. 4, April 2017. DESE, Indian Institute of Science, Bangalore, India

  9. Neutral Point Voltage Deviation • NPC and stacked MLI suffer from the problem of neutral point voltage deviations in case of single DC-link operation. • Consider for a 3-level NPC, for a reference voltage Vx (-1<Vx<1), where, x =A, B, C, the duty ratios for output pole voltage levels k (k = 1, 0, -1) are given as = = = = • This shows the average neutral point current (INP) in a switching interval. • This causes neutral point deviation in DC-link stacked capacitor. DESE, Indian Institute of Science, Bangalore, India

  10. Open End Induction Motor (OEIM) Drives Fig: 2-level dual fed Induction motor drives Two, 2-level structure from both sides will results in 3-level hexagonal voltage space vector structure DESE, Indian Institute of Science, Bangalore, India

  11. OEIM Drives Using Single DC-link Fig: 3-level Common mode eliminated OEIM drive Two, 2-level common mode eliminated structure combined together to give 3-level common mode eliminated structure DESE, Indian Institute of Science, Bangalore, India

  12. OEIM Drives Using Single DC-link • Generates 7-level common mode eliminated structure. • Has two 7-level inverter from both sides • Uses three isolated DC-sources [1] [1] G. Mondal, K. Sivakumar, R. Ramchand, K.Gopakumar, and E. Levi, “A dual seven-level inverter supply for an open-end winding induction motor drive,” IEEE Transactions on Industrial Electronics, vol. 56, no. 5, pp. 1665–1673, May 2009. Fig: 7-level Common mode eliminated OEIM drive DESE, Indian Institute of Science, Bangalore, India

  13. Modulation Schemes Fig: Classification of modulation schemes DESE, Indian Institute of Science, Bangalore, India

  14. Harmonic Elimination and Suppression DESE, Indian Institute of Science, Bangalore, India • High frequency PWM • Higher switching losses • EMI issues • Good only in linear modulation range • Selective Harmonic Elimination PWM • Limited modulation range • Requires offline computations • Split-phase Induction machine • Low-order passive filters • More losses in the filters • Bulky, good for high frequency harmonics • DC-link utilization is poor • Voltage space vector structures with more number of sides like 12,18,24 ….

  15. Dodecagonal Voltage Space Vector Structure Fig: 2-level dodecagonal vector space DESE, Indian Institute of Science, Bangalore, India

  16. Features of Dodecagonal Space Vector Structures DESE, Indian Institute of Science, Bangalore, India Absence of 6n+/-1(where n is odd) harmonic from motor phase voltage. Thus, low order 5th and 7th harmonics is absent from motor phase voltage. Requirement of low order filter is reduced. Absence of 6th harmonic torque ripple. Increase of linear modulation index from 45.5 Hz to 48.3 Hz for a 50Hz system.

  17. Generation of Dodecagon Using Single DC Link • Two inverters are required namely primary and secondary inverter. • If the dodecagon is formed such that radius is 0.966Vdc.[1] • Pseudo vector(H1) is 0.259<105>,Which can be obtained by switching 3S:2S in the ratio of 0.732:0.268 • Whole active power is provided by primary inverter • Capacitor is used to feed the secondary inverter [1] S.Pramanick, R.S. Kaarthik, N.A. Azeez, K. Gopakumar, S.S.Williamson and K.S. Rajasekhara “A harmonic suppression scheme for full speed range of a two-level inverter fed Induction Motor drive using switched capacitive filter,” IEEE Trans.Power Electron., vol. 32, no. 3, pp. 2064–2071, March 2017. DESE, Indian Institute of Science, Bangalore, India

  18. Multilevel Dodecagonal Structures Using Single DC-link • Utilizes advantages of both multilevel and dodecagonal space vector structures[1]. • Getting 6 concentric dodecagonal space vector structure.[1] [1] M. Boby, S. Pramanick, R.S. Kaarthik, A.R.S, K. Gopakumar and L. Umanand, “Fifth and seventh-order harmonic elimination with multilevel dodecagonal voltage space vector structure for IM drive using a single DC source for the full speed range” IEEE Trans.Power Electron., vol. 32, no. 1, pp. 60-68, Jan 2017.0 DESE, Indian Institute of Science, Bangalore, India Fig: (a) Power circuit topology, (b) space vector structure

  19. Motivation for Research DESE, Indian Institute of Science, Bangalore, India Can a method be developed to restrict the neutral point voltage deviation for any n-level stacked MLI ? Method need to be independent of loading, load power factor, modulation index ? To develop new multilevel inverter topology with optimum component count and having stacked and cascaded basic inverter cells ? Can multilevel dodecagonal structure be obtained with more no. of levels from both side using more than one capacitor fed CHBs in secondary inverter and power sourcing from one inverter? Can independent balancing of more than one capacitors on secondary inverter possible ? Is Multilevel dodecagonal structure possible with stacked inverter at the primary, which makes it one of the solution where stacking of low voltage batteries are required ?

  20. Instantaneous Neutral Point Voltage Control for Stacked DC-link Capacitor of Multilevel Inverter Using Dual Fed Induction Motor Drive DESE, Indian Institute of Science, Bangalore, India

  21. Overview DESE, Indian Institute of Science, Bangalore, India Neutral point voltage (NPV) balancing method using symmetrical 6-phase induction motor (IM). Topology used to validate the method. NPV control along with CHB capacitor voltage balancing. Common mode voltage eliminated 7-level structure generation along with NPV control Generalization of method Implementation Results Conclusion

  22. NPV Balancing Using Symmetrical 6-phase IM Fig: Windings of symmetrical 6-phase IM DESE, Indian Institute of Science, Bangalore, India Symmetrical 6-phase has all the six windings displaced by 600 from the adjacent one. Forms the three set of opposite phase pairs (A-A’, B-B’, C-C’). In order to aid the air-gap flux both opposite phases need to be modulated 180o phase shifted signals. Thus, opposite phase pair has equal and opposite phase currents Also, reduces the DC link requirement by Vdc/2.

  23. Topology Used for NPV Control • Switches(S1,S2,SC,SD) has to be rated for Vdc/6, switches (SA,SB) has to be rated for Vdc/12. Switches(S3) has to be rated for 2Vdc/6. • 7-level structure is possible. While, CHB-2 is used for neutral point balancing DESE, Indian Institute of Science, Bangalore, India Fig: Proposed 7-level inverter topology along with instantaneous control of neutral point voltages

  24. Combination of Stacked Inverter and CHB1 Table : Switching state redundancies Note: x = A, B, C • Stacked inverter and CHB1 are capable of generating seven pole voltage levels. • But, draws current from neutral points (O1, O2) while generating different pole voltage levels. DESE, Indian Institute of Science, Bangalore, India

  25. Neutral Point Currents • H1x : indicates whether neutral point O1 is used for generating particular pole voltage level from the phase. ‘1’ means inverter in phase uses neutral point ‘O1’ otherwise ‘0’. • H2x : indicates whether neutral point O2 is used for generating particular pole voltage level from the phase. ‘1’ means inverter in phase uses neutral point ‘O2’ otherwise ‘0’. • Thus the current drawn from neutral points are Where, IA, IB, IC are the A, B, C phase currents. • This shows that the NPV control is not possible. DESE, Indian Institute of Science, Bangalore, India

  26. Neutral Point Voltage Control • The opposite phase pairs in symmetrical 6-phase IM are at equal and opposite pole voltage levels. This causes equal and opposite phase currents. For example, if A-phase is at pole voltage level ‘1’, the A’-phase will be at pole voltage level ‘-1’. • This property of equal and opposite currents in opposite phase pairs of can be utilized. • If the opposite phase pairs are connected to same neutral point, there will be instantaneous cancellation of current drawn by opposite phases from neutral point. • But, when the combination of stacked inverter and CHB1 is used, the upper levels (‘2’, ‘1’) can only be connected to either DC bus +ve or neutral point O1. Similarly, lower levels (‘-1’, ‘-2’) can be connected to either DC bus –ve or neutral point O2. • The use of CHB2 with voltage Vdc/6 in each phase enables opposite phases to connect to both the neutral points (‘O1’, ‘O2’) when the required levels are ‘2’, ‘1’, ‘0’, ‘-1’, ‘-2’. DESE, Indian Institute of Science, Bangalore, India

  27. Pole Voltage Redundancies DESE, Indian Institute of Science, Bangalore, India

  28. CHB and DC-link Stacked Capacitor Voltage Balancing • Each inverter (INV1 and INV1’) will be assigned as master and slave inverter in alternate sampling duration. • The inverter which is assigned as master inverter, chooses the switching state so as to balance the CHB capacitors (C1x, C2x ) in the phases of master inverter. • The slave inverter is forced to choose such switching state which enables both the opposite phases to connect to the same neutral point. • But this results in undesirable deviation of CHB capacitor voltages (C1x, C2x) in the phases of slave inverter. • This will be balanced in next sampling duration when the slave inverter becomes master and vice-versa. • Thus, CHB capacitors (C1x, C2x) in the INV1 and INV1’ need to be designed for two sampling durations. DESE, Indian Institute of Science, Bangalore, India Fig: Inverter status

  29. Capacitor Balancing and NPV Control DESE, Indian Institute of Science, Bangalore, India A-phase is generating pole voltage of 2Vdc/12 (‘2’) while A’-phase is generating a pole voltage of -2Vdc/12 (‘-2’). The INV1 is master and INV1’ is slave inverter

  30. Capacitor Balancing and NPV Control DESE, Indian Institute of Science, Bangalore, India A-phase is generating pole voltage of 2Vdc/12 (‘2’) while A’-phase is generating a pole voltage of -2Vdc/12 (‘-2’). The INV1 is master and INV1’ is slave inverter

  31. Common Mode Eliminated 7-level Space Vector Generation with NPV Control • The single DC link operation of dual fed inverter system for open end induction motor (OEIM) require both the inverter to be operated with zero common mode voltage (CMV). • This is to avoid the flow of high frequency common mode currents in the power circuit. • The multilevel common mode structure reported in literature so far, need multiple isolated DC sources [1]. • The 7-level common mode eliminated structure with neutral point voltage control is proposed which enables the use of single isolated DC source with stacked capacitors. [1] G. Mondal, K. Sivakumar, R. Ramchand, K.Gopakumar, and E. Levi, “A dual seven-level inverter supply for an open-end winding induction motor drive,” IEEE Transactions on Industrial Electronics, vol. 56, no. 5, pp. 1665–1673, May 2009. DESE, Indian Institute of Science, Bangalore, India

  32. Topology to Generate 7-level Common Mode Eliminated structure with NPV control DESE, Indian Institute of Science, Bangalore, India Fig: Proposed 7-level common mode voltage eliminated inverter topology along with instantaneous control of neutral point voltages

  33. Topology Contd… • The topology has two 7-level inverters feeding from both the sides of induction machine. • Each 7-level structure has 4-level (37 space vector locations) has zero common mode voltage (with respect to point ‘O’ ) . • The two 4-level structure with zero common mode voltage from both sides combined together to give 7-level common mode eliminated. • The overall 13-level voltage space vector is generated but due to single DC-link operation only 7-levels can be used. • The linear modulation range is reduced to 78.4% as compared to 90.6% for the hexagonal space vector structure. DESE, Indian Institute of Science, Bangalore, India

  34. Generation of 7-level Common Mode Eliminated structure DESE, Indian Institute of Science, Bangalore, India Fig: 7-level common mode voltage eliminated space

  35. Switching State Combinations DESE, Indian Institute of Science, Bangalore, India

  36. CHB Capacitor Balancing and NPV Control • In this case also, one among the two inverter (INV1 and INV1’) will be assigned as master and slave inverter in alternate sampling duration. • The inverter which is assigned as master inverter, chooses the switching state so as to balance the CHB capacitors (C1x, C2x ) in the phases of master inverter. • The slave inverter is forced to choose such switching state which enables both the opposite phases to connect to the same neutral point. • The capacitors in slave inverter will be balanced will be balanced in next sampling duration when the slave inverter becomes master and vice-versa. • Thus, CHB capacitors (C1x, C2x) in the INV1 and INV1’ need to be designed for two sampling durations. DESE, Indian Institute of Science, Bangalore, India

  37. CHB Capacitor Balancing and NPV Control Contd… • The vectors from both ends may not be exactly 1800 . Thus, opposite phase pairs may not be at the opposite pole voltage levels. • For example, vector location B1 can be realized by switching state combination (2,-2,0) and (-3,0,3) applied from INV1 and INV1’. • The NPV control is achieved along with CHB capacitor voltage balancing by using switching state redundancies and pole voltage redundancies. For example, • In one sampling duration, while generating vector location B2, the combinations (2,0,-2) from INV1(master) and (-3,1,2) from INV1’ (slave) can be used. The CHB capacitors of A, B, C phase will be balanced, while NPV control is achieved by forcing A’, B’, C’ phase of INV1’ to connect to same neutral point. • In the next sampling duration, while generating vector location B2, the combinations (3,0,-3) from INV1(slave) and (-2,1,1) from INV1’ (master) can be used. The CHB capacitors of A’, B’, C’ phase will be balanced, while NPV control is achieved by forcing A, B, C phase of INV1 to connect to same neutral point. DESE, Indian Institute of Science, Bangalore, India

  38. Generalization of Method • If there are ‘n’ stacks in stacked MLI, the NPV can be controlled using ‘x’ no. of CHBs in each phase of symmetrical 6-phase IM or OEIM, where ‘x’ is given as x = n-1/2, if ‘n’ is odd ; x = n-2/2, if ‘n’ is even The CHBs are capacitor fed and are maintained at the voltage of Vdc/2n DESE, Indian Institute of Science, Bangalore, India Fig: (a) Topology with three stacks, (b) Topology with four stacks

  39. PWM Implementation - Symmetrical 6-phase IM • Level shifted carrier based SVPWM is used. Fig: Level shifted carrier SVPWM for 7-level inverter Fig: Block diagram for level shifted carrier based SVPWM DESE, Indian Institute of Science, Bangalore, India

  40. PWM Implementation - OEIM + j = = = + j + + = + Fig: Block diagram for PWM Implementation DESE, Indian Institute of Science, Bangalore, India

  41. Hardware Implementation Fig: Hardware implementation block diagram DESE, Indian Institute of Science, Bangalore, India

  42. Hardware Implementation Contd… Fig: Hardware implementation • 3-phase, 415V, 15kW, 50Hz IM is used • No-load Test is done • With DC link (Vdc) of 200V DESE, Indian Institute of Science, Bangalore, India

  43. Steady State Result with Symmetrical 6-Phase IM – 45Hz and 30Hz Steady state experiment result for 45Hz and 30Hz operation: (a) 45Hz operation; Top to bottom: (1) A-A' phase voltage (VAnand VA‘n, 100V/div), (2) pole voltage of A- phase(VAN, 100V/div), (3) pole voltage of A’- phase(VA’N, 100V/div), (4) A-A' phase current (IAand IA’, 5A/div);X-axis = 5ms/div; (b) 30Hz operation; Top to bottom: (1) A-A' phase voltage (VAn and VA‘n , 100V/div), (2) pole voltage of A- phase(VAN, 100V/div), (3) pole voltage of A’- phase(VA’N , 100V/div), (4) A-A' phase current (IA and IA‘ , 5A/div); X-axis = 10ms/div; DESE, Indian Institute of Science, Bangalore, India

  44. Steady State Result with Symmetrical 6-phase IM – 20Hz and 10Hz Steady state experiment result for 20Hz and 10Hz operation: (a) 20Hz operation; Top to bottom: (1) A-A' phase voltage (VAnand VA‘n, 100V/div), (2) pole voltage of A- phase(VAN, 100V/div), (3) pole voltage of A’- phase(VA’N, 100V/div), (4) A-A' phase current (IAand IA’, 5A/div);X-axis = 10ms/div; (b) 30Hz operation; Top to bottom: (1) A-A' phase voltage (VAn and VA‘n , 50V/div), (2) pole voltage of A- phase(VAN, 50V/div), (3) pole voltage of A’- phase(VA’N , 50V/div), (4) A-A' phase current (IA and IA‘ , 5A/div); X-axis = 20ms/div; DESE, Indian Institute of Science, Bangalore, India

  45. Steady State Result with Neutral Point Current for Symmetrical 6-phase IM – 45Hz Experiment result for 45Hz operation with neutral point currents: (a) Top to bottom: (1) A-phase voltage (VAN,100V/div), (2) Current drawn by A'-phase from neutral point O1 (3A/div) , (3) Current drawn by A-phase from neutral point O1 (3A/div), (4) A-phase current (5A/div) ; (b) Top to bottom: (1) A-phase voltage (VAN, 100V/div), (2) Current drawn by A'-phase from neutral point O2 (3A/div) , (3) Current drawn by A-phase from neutral point O2 (3A/div), (4) A-phase current (5A/div); X-axis = 5ms/div DESE, Indian Institute of Science, Bangalore, India

  46. Steady State Result with Neutral Point Current for Symmetrical 6-phase IM – 30Hz Experiment result for 30Hz operation with neutral point currents: (a) Top to bottom: (1) A-phase voltage (VAN,100V/div), (2) Current drawn by A'-phase from neutral point O1 (3A/div) , (3) Current drawn by A-phase from neutral point O1 (3A/div), (4) A-phase current (5A/div) ; (b) Top to bottom: (1) A-phase voltage (VAN, 100V/div), (2) Current drawn by A'-phase from neutral point O2 (3A/div) , (3) Current drawn by A-phase from neutral point O2 (3A/div), (4) A-phase current (5A/div); X-axis = 10ms/div DESE, Indian Institute of Science, Bangalore, India

  47. Transient Result with Symmetrical 6-phase IM - Acceleration Experimental results for acceleration from 15Hz to 40Hz:(a) Top to bottom: (1) Motor phase voltage (VAn, 50V/div), (2) C2A capacitor voltage (VC2A, 50V/div), (3) C1A capacitor voltage (VC1A, 20V/div),(4) Motor phase current (IA, 5A/div);(b) Top to bottom: (1) Motor phase voltage (VAn, 50V/div), (2) Current drawn from neutral point O1 (5A/div), (3) Current drawn from neutral point O2 (5A/div),(4) Motor phase current (IA, 5A/div); X-axis = 2s/div DESE, Indian Institute of Science, Bangalore, India

  48. Transient Result with Symmetrical 6-phase IM – Starting and Disturbance Transient results for motor starting and capacitor algorithm testing (a) Motor starting at 30Hz: Top to bottom: (1)Motor phase voltage (VAn, 50V/div), (2) C2A capacitor voltage (VC2A, 50V/div), (3) C1A capacitor voltage (VC1A, 20V/div),(4) Motor phase current (IA, 5A/div); X-axis = 2s/div; (b) Intentionally unbalancing of capacitor voltage at 30Hz: Top to bottom: (1) Motor phase voltage (VAn, 50V/div), (2) C2A capacitor voltage (VC2A, 20V/div), (3) C1A capacitor voltage (VC1A, 20V/div),(4) Motor phase current (IA, 5A/div); X-axis = 1s/div DESE, Indian Institute of Science, Bangalore, India

  49. Steady State Result with OEIM – 39Hz and 30Hz Steady state experiment result for 39Hz and 30 Hz operation with OEIM : (a) for 39Hz operation: Top to bottom: Motor phase voltage (VAA', 100V/div), (2) A-phase pole voltage (VAN, 100V/div), (3) A'-phase pole voltage (VA'N, 100V/div), (4) Motor phase current (IA, 10A/div), (5) Common mode voltage (CMV11', 50V/div); X-axis = 5ms/div; (b) for 30Hz operation: Top to bottom: Motor phase voltage (VAA', 100V/div), (2) A-phase pole voltage (VAN, 100V/div), (3) A'-phase pole voltage (VA'N, 100V/div), (4) Motor phase current (IA, 10A/div), (5) Common mode voltage (CMV11', 50V/div); X-axis = 10ms/div; DESE, Indian Institute of Science, Bangalore, India

  50. Steady State Result with OEIM – 20Hz and 10Hz Steady state experiment result for 39Hz and 30 Hz operation with OEIM : (a) for 39Hz operation: Top to bottom: Motor phase voltage (VAA', 100V/div), (2) A-phase pole voltage (VAN, 100V/div), (3) A'-phase pole voltage (VA'N, 100V/div), (4) Motor phase current (IA, 10A/div), (5) Common mode voltage (CMV11', 50V/div); X-axis = 5ms/div; (b) for 30Hz operation: Top to bottom: Motor phase voltage (VAA', 100V/div), (2) A-phase pole voltage (VAN, 100V/div), (3) A'-phase pole voltage (VA'N, 100V/div), (4) Motor phase current (IA, 10A/div), (5) Common mode voltage (CMV11', 50V/div); X-axis = 10ms/div; DESE, Indian Institute of Science, Bangalore, India

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