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Measurement of the latest Tesla wafers at Udine

Measurement of the latest Tesla wafers at Udine. Summary by Diego Cauz on behalf of the Udine Group 12 th February 2003. New Tesla wafers. We have received 4 Tesla wafers from 2 batches in February: 8414-14, 8414-16, 8697-04, 8697-10. February. Visual inspection (VIS).

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Measurement of the latest Tesla wafers at Udine

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  1. Measurement of the latest Tesla wafers at Udine Summary by Diego Cauz on behalf of the Udine Group 12th February 2003

  2. New Tesla wafers • We have received 4 Tesla wafers from 2 batches in February: • 8414-14, 8414-16, 8697-04, 8697-10

  3. February Visual inspection (VIS) mask align (H-V) ID marking Wafer n-side L n-side R p-side Lp-side R • 8414-144-44-44-44-4correct • 8414-164-44-44-44-4 correct • 8697-044-44-44-44-4 correct • 8697-104-44-44-44-4 correct • Legenda: • “4” means that the 4th vernier (ME-PASS) has problems, • specifically the passivation part. • -Normal face means lines are bad • -Boldface means very bad lines (as sampled on the • next two slides) or lines missing altogether.

  4. Wafer 8697-10 4th pair, horizontal

  5. Wafer 8697-10 4th pair, vertical

  6. February I-V on diode w/ guard ring (IVD) Wafer Vbd (V) Iop(nA) • 8414-14500 2.73 • 8414-16500 5.78 • 8697-04500 5.29 • 8697-10500 3.16 Vbd = max V(I < 25 nA) Iop = I(Vop)

  7. February C-V on diode w/ guard ring (CVD) 30 < Vdep (V) < 120 2000 < r (W cm) < 5000 Wafer Vdep Cdep Vop r (V) (pF) (V) (W cm) • 8414-14100 3.6 150 2207 • 8414-1690 3.7 150 2414 • 8697-04105 3.7 155 2045 • 8697-10105 3.7 155 2090 Vdep = V(kink in C-V curve) Cdep = C(Vdep) Vop = max(150 V, Vdep + 50 V)

  8. I-V on tiles February Vbd > Vop S = I(Vop) / I(Vop-50) < 2 Wafer Vbd (V) S goodtiles • 8414-1470 500 500 - 1.06 1.06 2 • 8414-16500 500 490 1.09 1.05 1.05 3 • 8697-0410 500 500 - 1.05 1.05 2 • 8697-1060 500 500 - 1.04 1.07 2

  9. I-V on SC’s: percent yield February Vbd > Vop S = I(Vop) / I(Vop-50) < 2 Wafer good/total • 8414-145/6 • 8414-166/6 • 8697-046/6 • 8697-105/6 Total: 91.7 %

  10. I-V on MC’s: percent yield February Vbd > Vop S = I(Vop) / I(Vop-50) < 2 Wafer good/total • 8414-14 4/4 • 8414-164/4 • 8697-044/4 • 8697-104/4 Total: 100 %

  11. I-t on good tiles (ITS) February S = Iend / Istart < 1.3 • 8414-14-02 1.1 • 8697-10-02 1.05 Wafer-tile S

  12. February I-V on MOS (BOX) Vbd > 50 V Vbd = max V(I < 100 pA) > 50 V regular delay = 2 s • 8414-14100 8 • 8414-16100 8 • 8697-04100 8 • 8697-10100 8 Wafer Vbd (V) delay (s) But funny shapes in three over four cases: see next slide

  13. The test is passed, but the shape is not very nice

  14. C-V on MOS (COX) February Cox = Cmax VFB = V(C nearest to CFB) • 8414-14278 5.1 53.1 4 • 8414-16273 5.5 62.6 4 • 8697-04274 5.2 54.5 4 • 8697-10269 5.2 53.8 4 Wafer Cox (pF) Cmin (pF) CFB (pF) VFB (V)

  15. I-V on gate-controlled diode (IVG) February Itop = I(VFB +3 V) Ibot = I(VFB – 3 V) Wafer Itop (pA) Ibot (pA) Iox(pA) • 8414-14282 24.3 258 • 8414-16862 53.8 808 • 8697-04414 17.7 369 • 8697-10482 15.0 467

  16. I-V on MOSFET (MFE) February Wafer Vth p dose (V) (1012 cm-2) • 8414-1430 2.95 • 8414-1630 2.90 • 8697-0430 2.91 • 8697-1030 2.85 Vth = max V(I < 100 nA) > 0 2.2 < p (1012 cm-2) < 3.5 But funny shapes in twoe over four cases: see next slide

  17. The test is passed, but there is that funny spike

  18. Vpix-V on punch-thru structure (PUT) February Wafer Vpt (V) • 8414-142.92 • 8414-162.08 • 8697-042.35 • 8697-102.50 Vpt = Vpix(Vop) > 3 V

  19. Planarity measurement (PLA) February Wafer aplanarity (mm) • 8414-14 8.4 • 8414-16 11.8 • 8697-04 9.0 • 8697-10 25.5 A < 40 mm

  20. Conclusions • Generally the measurements are good, with the following exceptions: • VIS: the passivation lines of the 4th verniers in the mask alignment pad are very poorly done. • BOX, MFE: funny shape of the data. • PUT: punch-through voltage is less than 3 V, but this can be due to the known problems we have with this measurement.

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