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MODERN 1 st Year Review ENIAC-120003 MODERN Ref. Technical Annex MODERN_PartB Rev2 v2.4

MODERN 1 st Year Review ENIAC-120003 MODERN Ref. Technical Annex MODERN_PartB Rev2 v2.4. WP1: Giuliana Gangemi WP2: Andr é Juge WP3: Wilmar Heuvelman WP4: Davide Pandini WP5: Loris Vendrame Coordinator: Jan van Gerwen Date: June 22, 2010 (09.30 - 17.00 hrs)

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MODERN 1 st Year Review ENIAC-120003 MODERN Ref. Technical Annex MODERN_PartB Rev2 v2.4

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  1. MODERN 1st Year Review ENIAC-120003 MODERNRef. Technical Annex MODERN_PartB Rev2 v2.4 WP1: Giuliana Gangemi WP2: André Juge WP3: Wilmar Heuvelman WP4: Davide Pandini WP5: Loris Vendrame Coordinator: Jan van Gerwen Date: June 22, 2010 (09.30 - 17.00 hrs) Review period: 2009-03-01 : 2010-02-28

  2. Agenda • General information (JvG) • Objectives • Consortium • Resources planned and used • Overview of deliverables and milestones status • Cooperation, dissemination and exploitation • Project management: progress, funding problems and amendments • Other issues, Q&A • For WP1 (GG), WP2 (AJ), WP3 (WH), WP4 (DP) and WP5 (LV) • Relationship between workpackages • Progress, highlights and lowlights • Technical status and achievements of deliverables (incl. changes) • Cooperation • Dissemination (publications, patents), exploitation • Other issues, Q&A MODERN 1st Year Review June 22, 2010

  3. WP5: Relationship between workpackages MODERN 1st Year Review June 22, 2010

  4. WP5: Progress, high- and lowlights WP5: Test structures and demonstrators 3 tasks: “test structures”, “hw demonstrators”, “sw demonstrators” Strong dependencies from WP 2,3,4:-close the loop also directly to each WP (efficiency)-‘light’ structure for WP5 -in depth result analysis done in respective WP -WP5 deliverables: list and description of activities and result summary . First year: 3 deliverables (one per task)released on schedule major results and technical achievements discussed in the following MODERN 1st Year Review June 22, 2010

  5. WP5: T5.1 Technical status, D5.1.1 achievements Task T5.1: Test structures for PV analysis: design, implementation and characterization Partners:AMS, NMX, STF2, TUGI First year goals: -critical review of state of the art test structure for inter and intra die variability-possible improvements All task partners involved in D.5.1.1 “Review of Test Structure State of the Art and First Results on Inter-Die Variability and Matching Characterization on Available Structures in Different Technology Nodes” Technology involved: 0.35um HVCMOS working up to 120V (AMS)45nm CMOS (STM)NonVolatileMemory 1.8V (NMX) partner complementarity mismatch MODERN 1st Year Review June 22, 2010

  6. NMOS 20V NMOS 50V NMOS 20V Option to measure without Gate-Protection 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Drain 40 0.7 Drain 10 0.7 Drain 1000 0.7 Drain 40 10 Drain 40 0.7 Drain 40 10 Drain 10 0.5 Drain 1000 0.5 Drain 40 0.5 Source Bulk Gate Sub Bulk Source n+ p well in n well Gate Protection AMS-TUGI standard and Kelvin probe measurement technique Accuracy vs.pad-count MODERN 1st Year Review June 22, 2010

  7. AMS-TUGI Transistor (W/L=40/0.5 um/um) threshold voltage offset ΔVTH=VTH1-VTH2lot-to-lot wafer-to-wafer MODERN 1st Year Review June 22, 2010

  8. STF2 Classical vs. Kelvin type Mismatch Test-Structures Biasing algorithm and results MODERN 1st Year Review June 22, 2010

  9. NMX: Combined Mismatch Test-Structures Same structure for mosfets and poly-gate resistance mismatch (possible detection: layout impact, systematic/stochastic effects, process impact) dummy on mos1 and mos2 dummy on mos2 onlyL of mos2 slightly changes MODERN 1st Year Review June 22, 2010

  10. WP5: T5.2 Technical status, D5.2.1 achievements Task T5.2: Demonstrator: design, implementation and characterization Partners:IFXA, NXP, UPC, THL, TMPO, LETI, TUGI, AMS First year goals: general preparatory activities for hw demonstrators and basic concept verification for noise, compensation and other test-chip architectures. IFXA and NXP partners involved in D.5.2.1 “Basic concept verification of noise, compensation, test chip architectures”. Other partners:-AMS and TUG: preparatory definition of benchmark cases and tools for PV aware and lifetime-critical device models of WP2-LETI: preliminary steps to implement on silicon (32 nm) a Local Adaptive Voltage and Frequency Scaling (LAVFS) architecture based on WP3 and WP4 developments; principle Vdd-Hopping' technique, major activities on analog sub-bloks for actuators, PVT sensors and timing slack monitors in 32 nm -UPC: preparatory activities to design single supply voltage level shifters and regular digital structures from WP4-TIEMPO activities will start in the second year-THL activities in the next year MODERN 1st Year Review June 22, 2010

  11. IFXA: Monitor & Control (compensation) and test-chip architectures TC1: verification of aging simulations of WP3-T3.3 Two stages Miller compensated OP-AMP + stress&test measurement concept for fast transients (us….100s) Preliminary results: aging mainly generates offset and transient relaxation effects significantly impact the generated offset until a steady state is reached in the range of several seconds MODERN 1st Year Review June 22, 2010

  12. IFXA: Monitor & Control (compensation) and test-chip architectures TC2: Monitor & control concepts under development -array of matched devices that are biased with equal stress conditions-switch degradation monitor by ring-oscillators (degradation of resistance will decrease the frequency)-ADC concept including error correction Preparatory steps for TC3 VCO test-bench / disengageable VCO (ring aged acting as PLL) TC2 layouts and ring concepts MODERN 1st Year Review June 22, 2010

  13. NXP: Substrate Noise New test chip “Neptune 5”, 65nm CMOSFeatures:-complex radio front ends as victims-digital IO buffers as aggressors-various grounding strategies-impact of different seal rings (analogue and digital GNDs) contribution to the substrate noise coupling-metal and FIB options Previous work (MEDEA+ Robin): measured noise by sensors for different protections to be improved by deembedding techniques sensor MODERN 1st Year Review June 22, 2010

  14. WP5: T5.3 Technical status, D5.3.1 achievements Task T5.3: Software demonstrator and tool prototype Partners:SNPS, NXP, ST-I, THL Project goals: Demonstrations of TCAD and CAD prototype software tools to asses the methodologies and algorithms coming out from WP2/3/4. D5.3.1 “Report on Software prototype implementation of Model Order Reduction for Multiple Input Multiple Output systems of R, RC, RCL” by NXP only. Other partners:-ST-I activity from 2nd year-Thales: working on a pedestrian detection application to be used on top of the architecture developed in T4.3 to test the repairing capabilities with the fault scenarios from T4.5.-SNPS: preparation works (tool/methodology development for Sentaurus device, definition of benchmark structures, preparation of hardware data, testing) for next year activity; implementation of the Green’s Function method for geometrical fluctuation in 3D. Strong links with task T2.2. MODERN 1st Year Review June 22, 2010

  15. NXP: Model Order Reduction • Focus: Parametrized MOR that preserve sub-structure, accuracy and stability (passivity) • SparseMA: the proposed model approximation MODERN 1st Year Review June 22, 2010

  16. WP5: Cooperation WP leader: NMX -Coordination among WP leaders in general meetings and separate phone calls -Task on-line meetings with participation of WP4 leader: T5.1 January 2010, T5.2 December 2009, -Phone calls and emails contacts for the “day by day” activities -Dedicated phone calls and email for the “CMP” silicon (see later) -Strongest cooperation is within “national clusters” -LIRMM will participate to this WP through the cooperative activities they are involved in the other WPs. LIRMM is planning, for the second year, the design, in close cooperation with CEA/LETI, of a platform based on an array of processing elements, called Smart ModEm Processors (SMEP), interconnected by a Network-on-Chip MODERN 1st Year Review June 22, 2010

  17. WP5: Dissemination (publications, patents), exploitation • Publication in the framework of Modern • IFXA: F. Chouard, M. Fulde, D. Schmitt-Landsiedel, “Impact of Degradation Mechanisms on Analog Differential Amplifiers”, ESSCIRC Fringer Poster Session 2009;F. Chouard, Ch. Werner, M. Fulde, D. Schmitt-Landsiedel, “A Test Concept For Circuit Level Aging Demonstrated By A Differential Amplifier”, IEEE IRPS 2010 pp.826-830; • Modern publications: • NMX: L. Bortesi, L. Vendrame, G. Fontana,”Combined test structure for systematic and stochastic Mosfets and gate resistance process variation assessment”, IEEE ICMTS 2010, pp227-230. • Others: • LIRMM activities toward demonstrator, i.e. System MPSoC Platform, with task migration, failure analysis, power optimization considering variability effects: FPGA MPSoC platform developed, demonstration done during the University booth at DATE2009 and SAME2009 (ref. listed in WP4). MODERN 1st Year Review June 22, 2010

  18. WP5: Other issues, Q&A • Part on the silicon (partners linked to the French cluster) will be spinned using CMP facilities:- plans of silicon runs are not under control of the partners - “additional” external schedule to be carefully taken into account.- risk assessment delivered (D.6.1.3)- continuous monitoring is ongoing- safer solution: 65nm CMOS technology (not very aggressive but useful for concept and methodologies proof) MODERN 1st Year Review June 22, 2010

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