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Crossbar switches. By Alejandro Ayala. Hardware design. Show hardware design of several modern crossbar switches used for multiprocessing system on chip or multicore design. AMD Opteron Architecture [1]. Integrated N.Bridge Data & Command packets are separated. Intel Xeon 7500 [2].

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crossbar switches

Crossbar switches

By Alejandro Ayala

hardware design
Hardware design
  • Show hardware design of several modern crossbar switches used for multiprocessing system on chip or multicore design.
amd opteron architecture 1
AMD Opteron Architecture [1]
  • Integrated N.Bridge
  • Data & Command packets are separated
intel xeon 7500 cont
Intel Xeon 7500 (cont)
  • 8 port (each 80bit)
  • Intel QuickPath Interconnect communication
ultrasparc t2 4
UltraSPARC T2 [4]
  • pipeline crossbar
  • High-bandwidth
  • 8x9 xBar
    • Cores-Mem
    • Cores-I/O
ultrasparc t2 cont
UltraSparc T2 (cont)
  • Divided into two parts
    • PCX
    • CPX
  • PCX/CPX divided into two parts
    • Arbiter
      • Assigns by old age
    • Data slice
characteristics of the crossbar
Characteristics of the crossbar
  • Compare characteristics of several switches used in modern MPSoC design
  • Are the switches buffered or bufferless? Is buffering done at the input, output, or at each crosspoint? What is the size of the buffers? Why that much?
  • How is the crosspoint implemented? Are the crossbars pipelined? What is the size of the crossbar switch? What is the bandwidth?
amd opteron 1
AMD Opteron [1]
  • Buffers at Input
  • Size are allocated to optimize throughput
system request queue srq
System Request Queue (SRQ)
  • What is the System request queue in AMD64 Opteron, Athlon X2?
system request queue 1
System Request Queue [1]
  • Prioritizes the access from both cores to use the crossbar.
  • Prevents contention to memory/resources
knockout switch
Knockout switch
  • What is knockout switch?
knockout switch 3
Knockout switch [3]
  • Problem:
    • Fully connected switch (ie every input connects to every output)
    • Congestion at output – different input might want to talk to same output.
  • Solution:
    • Concentrator at output
    • Buffer
knockout switch14
Knockout switch

Bus Interface

references
References

[1] Pat Conway, Bill Hughes, "The AMD Opteron Northbridge Architecture," IEEE Micro, vol. 27, no. 2, pp. 10-21, Mar./Apr. 2007,doi:10.1109/MM.2007.43

[2] Intel Xeon Processor 7500 series Volume 2, Datasheet, March 2010

[3] Y. Yeh, M. Hluchyj, and A. Acampora, “The Knockout Switch: A

Simple, Modular Architecture for High-Performance Packet

Switching,” IEEE J. Selected Areas in Comm., vol. 5, no. 8, pp. 1274-

1287, Oct. 1987.

[4] U. G. Nawathe, et al.. “An 8-Core 64 Thread 64b Power-Efficient

SPARC SoC,” in IEEE International Solid-State Circuits Conference (ISSCC), Dig. Tech Papers, Feb. 2007, pp. 108-110.