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RoI Occupancies

RoI Occupancies. An attempt to put an upper limit on useful RoIs in any region. Motivation: CP RoIs. Well established fact: CPM-CMM backplane bandwidth limitation: 16 RoIs per CPM, 16 data bits per RoI = 256 bits Two times CPM-CMM at ~96 bits each = 192 bits

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RoI Occupancies

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  1. RoI Occupancies An attempt to put an upper limit on useful RoIs in any region RoI occupancies

  2. Motivation: CP RoIs • Well established fact: CPM-CMM backplane bandwidth limitation: • 16 RoIs per CPM, 16 data bits per RoI = 256 bits • Two times CPM-CMM at ~96 bits each = 192 bits • Methods of reducing data: • Reduce number of RoIs • Reduce or change data content • Combination of both of above • This talk addresses only option 1. • Several possibilities: which is less ‘lossy’ RoI occupancies

  3. Maximum RoI occupancies • For a region of n x m towers (or elements) • Absolute RoI limit is ( n x m / 4 ) • From local maximum criteria • Examples: • CP system: 50 x 64, maximum 800 • JEP system: 32 x 32, maximum 256 • CPM: 4 x 16, maximum 16 • JEM: 4 x 8, maximum 8 • CP Chip: 4 x 2, maximum 2 • But the maximum is very difficult to achieve • Can be done with a contrived pattern • Not likely in physics RoI occupancies

  4. Estimating Real Occupancies • Generate random signals over a specified region • Plus the necessary ‘environment’ • Random signals actually provide a realistic upper limit • Adding structure actually reduces RoI occupancy • Well that’s my gut feeling, and I have some evidence • Use standard RoI algorithm • Just look for local maximum • No cut on energy • Again, with real thresholds should obtain fewerRoIs • Count RoIs RoI occupancies

  5. Interesting sub-regions • Aim is to reduce CPM RoI data volume • Consider three RoI reduction options • Sam’s scheme • CP chip (4x2), reduce 2 RoIs to 1 • Half of CPM thresholds to each CP Merger (current layout) • Whole CPM (4x16), reduce 16 RoIs to 10 • Details of format left to reader (10x8 + 16 bits = 96 bits) • Half CPM (all thresholds) to each CP Merger • Left or Right of CPM (2x16), reduce 8 RoIs to 5 • Details of format left to reader (5x16 + 8 bits = 88bits) • Note: not an entirely fair comparison • The second two schemes entirely discard extra RoIs • Sam’s scheme retains some information about extra RoI • Final option requires small change to CP chip (others don’t) RoI occupancies

  6. How they compare RoI occupancies CP chip (4x2) Half-CPM (2x16) JEM (4x8) CPM (4x16) ‘Lost’ RoIs

  7. Let’s see that on a log scale! RoI occupancies CP chip (4x2) Half-CPM (2x16) JEM (4x8) CPM (4x16)

  8. Additional Factors • Proviso: all estimates are probably over-estimates • But at least made with the same model, so comparable • CP chip reduction: 2 RoIs to 1 • Occurs with about 5% frequency • Multiplied by 384 instances in CP system • Half-CPM reduction: 6+ RoIs to 5 • Occurs with about 0.1% frequency • Multiplied by 100 instances in CP system • Full-CPM reduction: 11+ RoIs to 10 • Occurs with about 0.0005% frequency • Multiplied by 48 instances in CP system • RoI Selection would probably resolve all losses in final option • If possible! • Choose 10 highest energyRoIs, other will be small (probably) • Lowest thresholds will saturate at 7 anyway, so small ones add nothing RoI occupancies

  9. For interest: system sums • JEP system • Theoreticalmax 256 • Realistic max 100 • Average ~75 • CP system • Theoretical max 800 • Realistic max 280 • Average ~230 RoI occupancies

  10. Checking with real events: beam splashes • Like toy Monte-Carlo • Locally random • All local max form RoI (big energies) • Most of detector lit up • Good timing for ~75% of detector • Unlike toy Monte-Carlo • Contains structure • Famous 8-fold energy deposition • Random model would give: • ~170 CP RoIs, ~55 JEP RoIs • Actually get: • ~90 CP RoIs, ~30 JEP RoIs • Confirms: structure reduces RoI count RoI occupancies

  11. Conclusions • Probably an obvious conclusion • Increasing size of region considered reduces RoI loss • But still useful to put hard numbers on it • My preferred solution for standard 16 thresholds: • Keep CP chip as it is • Output 10 RoIs (plus RoI map) per CP merger chip • Ideally uses all 96 bits, but tricks are possible • Information/RoI loss is probablynegligible RoI occupancies

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