MOS Field-Effect Transistors (MOSFETs)

1. MOS Field-Effect Transistors (MOSFETs) 1

2. MOSFET ( Voltage Controlled Current Device) • MOS Metal Oxide Semiconductor Physical Structure • FET Field Effect Transistor The current controlled mechanism is based on an electric field established by the voltage applied to the control terminal – GATE • Uni-polar Current is conducted by only one carrier • IGFET Insulated Gate FET • CMOSFET Complementary MOSFET • 1930 was Known, 1960s Commercialized 1970s Most commonly used VLSI • NMOSFET/PMOSFET n/p-channel enhancement mode MOSFET

3. MOSFET • Small Size • Manufacturing process is simple • Requires comparatively low power • Implement digital & analog functions with a fewer resistors very large scale Integrated (VLSI) circuit • Study Includes • Physical structure • Operation • Terminal characteristics • Circuit Models • Basic Circuit application

4. Figure 4.1 Physical structure of the enhancement-type NMOS transistor:

5. Device Structure • Types “n” channel enhancement MOSFET “p” channel enhancement MOSFET • “n” Channel MOSFET • Fabricated on a p-type substance that provides physical support for the device. • Two heavily doped n-type region are created • n+ Source (‘S’) n+ for lightly doped ‘n’ type silicon • n+ Drain (‘D’) n+ for heavily doped ‘n’ type silicon • Area between source & Drain • Thin Layer of Silicon dioxide (SiO2) is grown with thicker of tox= 2-50 nanometers An excellent electrical insulator • Metal is deposited on top of the oxide layer to form the Gate electrode. Metal contact is made to Source & Drain and the substrate (Body)

6. Figure 4.1 Physical structure of the enhancement-type NMOS transistor Cross-section. Typically L = 0.1 to 3 mm, W = 0.2 to 100 mm, and the thickness of the oxide layer (tox) is in the range of 2 to 50 nm.

7. Device Structure • Four terminals • Source (S) • Gate (G) • Drain (D) • Body (B) • L Length of channel region W Width of the substrate tox Thickener of An oxide Layer

8. Device Structure • Metal oxide semiconductor - name is derived from its physical structure • Insulted – Gate FET (IGFET) – gate is electrically insulated from the device body • Current in gate terminal is small (10-15 A) • Substrate forms pn junctions with the source & drain region & is kept reversed biased all the time • Drain will be at a positive voltage relative to the source, two junctions are at cutoff mode if substrate is connected to the source. Thus Body will have no effect on operation of the device.

9. Principle of operation • Voltage applied to the Gate controls current flow between Source & Drain with direction from Drain to Source in channel region • It is a symmetrical device thus Drain & Source can be interchanged with no change in devices characteristics • With no bias gate voltage, two back-to-back diodes exist in series between drain and source. • No current flows even if vDSis applied. In fact the path between Source & Drain (1012Ω) has very high resistance

10. Figure 4.2 The enhancement-type NMOS transistor with a positive voltage applied to the gate. An n channel is induced at the top of the substrate beneath the gate.

11. Creating a Channel for Current Flow • Source & Drain are grounded and a positive voltage (vGS)is applied to the gate. • Holes are repelled-leaving behind a carrier depletion-region. • Depletion region is populated with the bounded negative charges associated with the acceptor atoms and are uncovered because the neutralizing holes have been push downward into the substrate.

12. Channel for Current Flow • Positive gate attracts electrons from the n+ source & drain region into the channel region. • Due to electrons accumulated under the gate, an ‘n’ region is created & connects source & drain region. • Thus if voltage is applied between source & drain, current flows due to mobile electrons between drain & source. • ‘n’ region forms a channel – ‘n’ channel MOSET (NMOSFET)

13. Channel for Current Flow • An ‘n’ channel MOSFET is formed in a ‘p’ type substrate. Known as “Inversion Layer”. • The value ofvGSthat causes sufficient number of mobile electrons to be accumulate in the channel region to form conducting channel is called threshold Voltage “Vt”. • Vtfor ‘n’ channel is positive & value is 0.5 to 1V

14. Channel for Current Flow • Gate & channel region form a parallel plate capacitor, with oxide layer as the capacitor dielectric. • Positive charge is accumulated on gate electrode & negative charge on channel electrode. • An electric field thus develops in the vertical direction. • Capacitor charge controls the current flow through the channel when a voltage vDSis applied. • Gate Channel

15. Figure 4.3An NMOS transistor with vGS > Vt and with a small vDS applied. The device acts as a resistance whose value is determined by vGS. Specifically, the channel conductance is proportional to vGS – Vt’ and thus iD is proportional to (vGS – Vt) vDS.

16. vDS is applied (vDS = 50mV) causes iD to flow through induced ‘n’ channel. Direction is opposite to that of the flow of negative charges. Magnitude ofiDdepends upon density of electrons and in term onvGS . vGS ≤ Vt Negligible current iD as the channel has been just induced. vGS > Vt iD current increases, increases conductance of the channel & is proportional to Excess gate voltage (vGS - Vt ) vGS - Vtis known as Excess gate Voltage , Effective Voltage Overdrive Voltage (VOV) MOSFET operatrates as a linear resistance whose value is controlled by vGS. vGS above Vt enhances the channel – named Enhanced Mode operation & enhanced type MOSFET iD = iS, iG = 0 Applying a Small vDS

17. Figure 4.4 The iD–vDS characteristics of the MOSFET When the voltage applied between drain and source, vDS, is kept small. The device operates as a linear resistor whose value is controlled by vGS.

18. Figure 4.5 Operation of the enhancement NMOS transistor as vDS is increased. The induced channel acquires a tapered shape, and its resistance increases as vDS is increased. Here, vGS is kept constant at a value > Vt.

19. The drain current iD versus the drain-to-source voltage vDS for an enhancement-type NMOS transistor operated with vGS > Vt.

20. Increasing vDS causes the channel to acquire a tapered shape. Eventually, as vDS reaches vGS – Vt’ the channel is pinched off at the drain end. Increasing vDS above vGS – Vt has little effect (theoretically, no effect) on the channel’s shape.

21. Derivation of the iD–vDS characteristic of the NMOS transistor.

22. Drain Current iD • Directly Proportional to: • Mobility of Electrons in the channel μn (μm2/V) • Gate Capacitance per unit gate area Cox (μF/ μm) • Width of the substrate (μm) • Gate-Source Voltage vGS(Volts) • Drain-Source Voltage v DS (Volts) • Indirectly Proportional to: • Length of the channel (μm)

23. iD – vDS relationship Troide Mode Saturation Mode

24. The p Channel MOSFET • Fabricated on an n-type substrate with p+ regions for Drain & Source • Holes are the current carriers. • vGS & vDS are negative • Threshold voltage Vt is negative. • Both NMOS & PMOS are utilized in Complementary MOS or CMOS circuits

25. Complementary MOS or CMOS Cross-section of a CMOS integrated circuit. Note that the PMOS transistor is formed in a separate n-type region, known as an n well. Another arrangement is also possible in which an n-type body is used and the n device is formed in a p well. Not shown are the connections made to the p-type body and to the n well; the latter functions as the body terminal for the p-channel device.

26. iD – vDS Charateristics • Modes of operation • Cutoff • Triode (Saturation in BJT) • Saturation ( Active in BJT)

27. The iD–vDS characteristics for a device with k’n (W/L) = 1.0 mA/V2.

28. The iD–vGS characteristic for an enhancement-type NMOS transistor in saturation (Vt = 1 V, k’nW/L = 1.0 mA/V2).

29. Large-signal equivalent-circuit model of an n-channel MOSFET operating in the saturation region.

30. Finite Output Resistance in Saturation Increasing vDS beyond vDSsat causes the channel pinch-off point to move slightly away from the drain, thus reducing the effective channel length (by DL).

31. Finite Output Resistance in Saturation Effect of vDS on iD in the saturation region. The MOSFET parameter VA depends on the process technology and, for a given process, is proportional to the channel length L.

32. Finite Output Resistance in Saturation Large-signal equivalent circuit model of the n-channel MOSFET in saturation, incorporating the output resistance ro. The output resistance models the linear dependence of iD on vDS

33. Circuit symbol for the p-channel enhancement-type MOSFET.

34. Characteristics of PMOSFETTriode Mode of Operation

35. Characteristics of PMOSFETSatuaration Mode of Operation

36. The Roll of Substrate :Body Effect • Substrate for many Transistors • Body is connected to the most negative power supply to maintain cutoff conditions for all the substrates to channel junctions • Another gate

37. Temperature Effects • Vt and K’n are effected by the temperature • Vtincreases by 2mV per 10C rise in temperature • K’ndecreases with rise in temperature thus drain current increases. The effect is dominant. Thus ID decreases with increase in temperature MOSFET in Power circuits

42. Graphical construction to determine the transfer characteristic of the amplifier in (a).

43. Circuit for Example 4.9.

45. Biasing the MOSFET using a large drain-to-gate feedback resistance, RG.

46. Biasing the MOSFET using a constant-current source

47. Conceptual circuit utilized to study the operation of the MOSFET as a small-signal amplifier.

48. Recap : Transfer Function

49. Transfer characteristic showing operation as an amplifier biased at point Q.

50. Conceptual circuit utilized to study the operation of the MOSFET as a small-signal amplifier. The DC BIAS POINT To Ensure Saturation-region Operation