ECE 353 Introduction to Microprocessor Systems

1. ECE 353Introduction to Microprocessor Systems Michael J. Schulte Week 10

2. Administrative • Reading for next week 10 • Supplement #3, review chapter 9 in text, • ADuC datasheet pages 79-82 • Homework #4 returned • Average of 85% • Still grading Quiz #2

3. Topics • ADuC7026 External Memory Interface • Implementation • Demultipexing • Bus Timing • Bus cycle timing modification • Wait states and more • Assessing timing compatibility

4. Basic System Bus Operation • Address • Unidirectional from CPU • Data • Bidirectional • Control • /RS or /RD – output from CPU • Indicates a read operation in progress • /WS or /WR – output from CPU • Indicates a write operation in progress • /WAIT or /READY – input to CPU • Used by external device to signal that it is not able to complete transfer yet

5. ADuC7026 Bus Operation • The ADuC7026 external memory interface consists of • 16-bit multiplexed address/data bus (AD15:0) • High address for 8-bit operation (A16) • Read and write strobes (/RS, /WS) • Memory select signals (/MS3:0) • Byte enables (/BHE, /BLE) • Demultiplexing control signal (AE) • There is no WAIT/READY signal • Basic Read Cycle Sequence at Bus Level • Diagram • Basic Write Cycle Sequence at Bus Level • Diagram

6. ADuC7026 Demultiplexing • Multiplexed Signal Timing • Read Cycle • Dealing with a multiplexed bus • Demultiplexing by the device • Demultiplexing logic to create an address bus • Implementation • Devices – latches or flip-flops • Connections • AE timing

7. SRAM Timing Compatibility • In order to properly read and write the device, we need to ensure that the processor-to-memory interface is compatible with the memory device. • This is accomplished by analyzing the timing for all relevant parameters, and ensuring that the operation can be completed successfully. • We will work through the read cycle analysis for the ADuC7026...

8. Assessing Timing Compatibility • Need to know whether CPU could operate with the tAA for given device. (read cycle) • We designate a CPU characteristic tAVDV, which is the delay from • When the address becomes valid at the CPU • Until the data must be driven to CPU • This establishes an upper bound on tAA • tAA < tAVDV • Read cycle parameters (see handout) • Read cycle timing control (see handout) • Simple Example

9. Address Valid to Data Valid Time (tAvdv) • If the fastest bus cycle is used then tAVDV = 3 CLK - tDATA_SETUP • If the bus cycle is extended then tAVDV = 3 CLK - tDATA_SETUP + (nAW + nAH + nRDTA + nW) CLK address wait states (nAW) – set by XMxPAR[14:12] (0-7) address hold time (nAH) – set by XMxPAR[10] (0-1) read turn-around time (nRDTA) – set by XMxPAR[9] (0-1) wait states (nW) – set by XMxPAR[3:0] (0-15) • There is an upper bound on tAA • tAA < tAVDV

10. System Timing Compatibility • Need to account for all delays in a system to assess timing compatibility. • Consider this system. • Analyze the read timing with regard to: • tAA – address access time • tACS – chip enable to valid data • tOE – output enable to valid data • tDF – output hold/float time • Read cycle timing control (see handout) • Information also in Supplement 3

11. Analyzing the address access time (tAA) • Before a valid address is available at the SRAM, it must and go through the latch after ½ clock cycle . This gives tAA < tAVDV - ½ CLK – tLATCH • Expanding tAVDV gives tAA < 2.5 CLK - tDATA_SETUP - tLATCH + (nAW + nAH + nRDTA + nW) CLK

12. Analyzing the chip enable access time (tCE) • The chip enable depends on /MSx, /BHE, /BHE and the address • The last signal to arrive at the decoder is the byte enables • The byte enables are asserted one cycle before the rising edge of /RS, which gives tCE < CLK - tDATA_SETUP – tDECODER • If the read cycle is lengthened then tCE < CLK – tDATA_SETUP – tDECODE_LOGIC + (nAH + nRDTA + nW) CLK • What happens for an 8-bit bus (no byte enables)?

13. Analyzing the output enable access time (tOE) • The SRAM /OE input is driven by the /RS signal • For the fastest bus cycle this gives tCE < CLK – tDATA_SETUP • If the read cycle is lengthened then tCE < CLK – tDATA_SETUP + (nW) CLK

14. Analyzing the data float time (tDF) • How long is the data guaranteed to be valid? Will it meet the hold time? • The data may go invalid if the address becomes invalid, or \CS or \OE go high. • Which occurs first? • Based on the read cycle parameters, we must guarantee tOHZmin > tDATA_HOLD • To ensure the SRAM stops driving before the processor drives the next address, we need tOHZMAX < CLK

15. ADuC7026 External Memory Interface Configuration • The external memory interface supports four independently configured memory regions, each of which is 128kB in size. • In order to use the external memory interface, we need to • Configure the required pins (GPxCON) • Enable the external interface (XMCFG[0] = 1) • Configure for bus width and enable the region (XMxCON) • Configure for the desired bus timing (XMxPAR)

16. ADuC7026 GPIO Ports • The ADuC7026 has 40 pins organized as 5 ports that can be used as digital GPIO • All pins have multiple functions in addition being able to be used as GPIO • The configuration selection is set through the GPxCON MMR.

17. ADuC7026 XMxCON • The XMxCON registers configure the bus width and enable the interface for the respective 128KB memory region. • XM0CON  0x10000000-0x1001FFFF • XM1CON  0x20000000-0x2001FFFF • XM2CON  0x30000000-0x3001FFFF • XM3CON  0x40000000-0x4001FFFF

18. Write cycle timing control Read cycle timing control ADuC7026 XMxPAR • The XMxPAR MMR configures the bus timing for a region • 0x70FF at reset • [14:12] – AE extend • [9] – implements bus turn-around • [8] – provides additional hold time • [7:4],[3:0] – extend write/read strobes

19. System Timing Compatibility • Consider again the system. • Analyzing write cycle timing. • SRAM write characteristics • tWC • tAS, tAW, tCW • tWR • tWDS, tWDH • Write cycle controls

20. Timing Wrap-Up • Device characteristics are just part of the total timing analysis picture • Line/device capacitive loading and driver slew rates • Transmission line effects and parasitic reactance • Impedance mismatch and reflections • Skew and physical/electrical trace length mismatch • Signal integrity • Ensuring that signals are correct in spite of all of the above issues and mutual coupling effects

21. Wrapping Up • Reading for next week 11 (interrupts and exceptions) • Textbook chapter 8 • ADuC 74-75 • ARM7 2.8-2.10

22. Basic Read Cycle

23. Basic Write Cycle

24. Read Cycle Parameters

25. Write Cycle Parameters

26. Read Cycle Controls nAW nAH nRDTA nW

27. Write Cycle Controls

28. 16-Bit Memory System