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ECE 353 Introduction to Microprocessor Systems

ECE 353 Introduction to Microprocessor Systems. Michael J. Schulte. Week 8. Topics. 80C188 system design Peripheral Control Block (PCB) Characteristics of ROM and RAM ICs Organization and operation of typical static RAM, EPROM and flash memory devices Memory subsystem design

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ECE 353 Introduction to Microprocessor Systems

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  1. ECE 353Introduction to Microprocessor Systems Michael J. Schulte Week 8

  2. Topics • 80C188 system design • Peripheral Control Block (PCB) • Characteristics of ROM and RAM ICs • Organization and operation of typical static RAM, EPROM and flash memory devices • Memory subsystem design • Address decoder implementation • 80C188EB Chip-Select Unit (CSU)

  3. 80C188EB System Design • Minimum-component system • PSD9XXF • Single and multi-board systems • Custom single board system • COTS Single Board Computer • Custom multi-board system • Multi-board standard bus system • SoC

  4. Peripheral Control Block (PCB) • Configuration, control and operation of the 80C188EB’s integrated peripherals • Diagram • 128 contiguous word registers • All PCB transfers are 16-bits over F-bus • External bus cycles are still run • At reset, PCB base address = FF00h in I/O • pcb.inc • Relocating the PCB • RELREG

  5. Memory Subsystems • ROM • Masked • OTP PROM • EPROM • EEPROM • Flash • RAM • SRAM • DRAM • Pseudo-SRAM • Flash – non volatile RAM

  6. Memory Organization • Logical organization • Organization as seen looking at the device from the outside • Linear array of registers (memory locations) • Physical organization • Different physical organizations can be used to implement the same logical organization • Physical organization affects performance and cost

  7. SRAM Interfaces • RAM with 3 control inputs • /CS, /OE, /WE • Read • Write • RAM with 2 control inputs • /CS, /WE (or R/W)

  8. SRAM Organization • Logical Organization • Typically 1, 4 , 8 or 16 bit widths • Physical Organization • Rectangular bit array • Two-level decoding (row and column) • Characteristic delays and timing requirements are specified in memory devices datasheet (Example) • NV-SRAM • Uses an alternate power source to maintain SRAM when system power is off • Requires logic to switch power sources and prevent spurious writes during power-up/power-down

  9. EPROM • Electrically programmable, non-volatile • Requires UV light to erase • Quartz window in package • Floating polysilicon gate avalanche injection MOS transistor (FAMOS) • Operation • Programmer loads device out-of-circuit • OTP EPROMs eliminate quartz window • EEPROMs are electrically erasable • Byte-erasable / writeable • Low-density • JEDEC Packages

  10. Flash Memory • Actually Flash EEPROM, commonly just called flash memory • Characteristics • Technologies • Endurance • Blocking, programming and erasing • Applications • ROM replacement • GP NV-RAM • Solid-state disk (flash-disk) Example

  11. Memory Subsystem Design • Memory banks • Increasing memory width • Increasing memory depth • Increasing memory width and depth • Address decoding • Exhaustive (full) vs. partial decoding • Granularity • Boundaries • If an address is a 2n boundary, then what is the result of (address AND (2n-1))?

  12. Memory Subsystems Review • What is the purpose of an address decoder circuit, and where does its output usually get connected? • What is exhaustive decoding, and what effects does it have? • What is partial decoding, and what effects does it have?

  13. 80C186EB Memory Subsystem • Organization • Logical • Physical • Word operations • Aligned words • Unaligned words • Byte operations • 80C186EB control signals • Byte-wide peripherals

  14. Memory Architectures • Wide (n-byte) buses • Addressing effects • Byte transfer support • Data lanes • Control signals • Bus resizing • Static • Configurable • Dynamic

  15. 80C188EB Chip Select Unit (CSU) • 10 programmable chip selects • /UCS, /LCS • /GCS0 - /GCS7 • Configuration • Active address range • Memory or I/O space • Wait states • Enable / disable • Use or ignore READY • Programming • Chip-Select Start Register • Chip-Select Stop Register

  16. External Address Decoders • SSI/MSI Decoders • Discrete gates • 1-of-n Decoders • 74xx138 • Partial decoding issues • PLD Decoders • PLAs • PALs • PALCE22V10

  17. PCB

  18. pcb.inc ;*********************************************** ;** I80C188 ** ;** ** ;** Peripheral Control Block ** ;** Include File for ** ;** I/O Mapping ** ;** ** ;*********************************************** PCBB EQU 0FF00H ; PCB Base Address ;Register Address INTRVEC EQU PCBB + 0020H ; Interrupt Vector Register INTRMSK EQU PCBB + 0028H ; Interrupt Mask Register PRIRMSK EQU PCBB + 002AH ; Priority Mask Register INSERV EQU PCBB + 002CH ; In-Service Register

  19. RELREG

  20. Chip-Select Start Reg

  21. Chip-Select Stop Register-Part 1

  22. Chip-Select Stop Register -Part 2

  23. Memory Organization

  24. Physical Organization

  25. JEDEC

  26. Flash Blocks

  27. Flash Memory Application:Disk-on-Key • Up to 1GB nonvolatile storage • No battery or power supply Specifications: Size: 85x28x15mm (LxWxH) Weight: 17g Data retention up to 10 years Power consumption: Write 36.0mA, Read 33.0mA Erase cycles: 1,000,000 times Read speed > 750KB / sec. Write speed >450 / sec. Shock resistance: 1000 G (maximum)

  28. PALCE22V10 Organization

  29. PALCE22V10 Macrocell

  30. RAM Read – 3 control signals

  31. RAM Write – 3 control signals

  32. Cypress PSoC

  33. Increasing Memory Depth

  34. Increasing Memory Width

  35. Increasing Memory Depth & Width

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