Topic 3c Integer Multiply and Divide

1. Topic 3cInteger Multiply and Divide Introduction to Computer Systems Engineering (CPEG 323) cpeg323-08F\Topic3c-323

2. Unsigned Integer Multiply • Paper and pencil example: Multiplicand1000Multiplier * 1001 1000 0000 00001000 Product 01001000 cpeg323-08F\Topic3c-323

3. 0 0 0 0 A3 A2 A1 A0 B0 A3 A2 A1 A0 B1 A3 A2 A1 A0 B2 A3 A2 A1 A0 B3 P7 P6 P5 P4 P3 P2 P1 P0 Observation • m bits * n bits = m+n bit product • Stage i accumulates A * 2 i if Bi == 1 cpeg323-08F\Topic3c-323

4. A3 A2 A1 A0 0 0 0 0 A3 A2 A1 A0 0 0 0 B0 A3 A2 A1 A0 B1 A3 A2 A1 A0 B2 B3 P7 P6 P5 P4 P3 P2 P1 P0 How does it work? • at each stage shift A left ( x 2) • use next bit of B to determine whether to add in shifted multiplicand • accumulate 2n bit partial product at each stage cpeg323-08F\Topic3c-323

5. Simple Mathematics A*B • If B has n bits, let the product be productn • 2i*A: shift A left for i times. • It is clear that multiply is composed of iterative • Shift and add Then when B has n+1 bits cpeg323-08F\Topic3c-323

6. Multiply hardware (V1) Shift Left Multiplicand 64 bits Multiplier 64-bit ALU 32 bits Shift Right Write Product Control 64 bits Note: The multiplicand, Product and ALU are all 64-bits, while the Multiplier is 32-bits. cpeg323-08F\Topic3c-323

7. Start Multiplier0=1 Multiplier0 = 0 1. Test Multiplier0 1a. Add multiplicand to product & place the result in Product register 2. Shift the Multiplicand register left 1 bit. 3. Shift the Multiplier register right 1 bit. 32nd repetition? No: < 32 repetitions Yes Done Multiply Algorithm (V1) cpeg323-08F\Topic3c-323

8. Observations on Multiply Version 1 • 1/2 bits in multiplicand always 0=> 64-bit adder is wasted • 0’s inserted in right of of multiplicand as shifted=> least significant bits of product never changed once formed • How many cycles it takes to multiply two 32-bit numbers ? cpeg323-08F\Topic3c-323

9. Instead of shifting multiplicand to left, shift product to right? cpeg323-08F\Topic3c-323

10. Multiply hardware (V2) Multiplicand 32 bits Multiplier 32-bit ALU 32 bits Shift right Shift Right Product Control Write 64 bits NOTE: Note: Only Product are 64-bits, while the rest are all 32-bits. cpeg323-08F\Topic3c-323

11. 1. Test Multiplier0 1a. Add multiplicand to the left half ofproduct & place the result in the left half of Product register Multiply Algorithm V2 Start Multiplier0=1 Multiplier0=0 2. Shift the Product register right 1 bit. 3. Shift the Multiplier register right 1 bit. 32nd repetition? No: < 32 repetitions Yes: 32 repetitions cpeg323-08F\Topic3c-323 Done

12. 0 0 0 0 A3 A2 A1 A0 B0 A3 A2 A1 A0 B1 A3 A2 A1 A0 B2 A3 A2 A1 A0 B3 P7 P6 P5 P4 P3 P2 P1 P0 What’s going on? • Multiplicand stay’s still and product moves right cpeg323-08F\Topic3c-323

13. Observations on Multiply Version 2 • Product register wastes space that exactly matches size of multiplier=> combine Multiplier register and Product register cpeg323-08F\Topic3c-323

14. Multiply hardware V3 Multiplicand 32 bits 32-bit ALU Shift right Product (Multiplier) Control Write 64 bits NOTE: now, the multiplier does need a separate register!! cpeg323-08F\Topic3c-323

15. 1. Test Product0 1a. Add multiplicand to the left half of product & place the result in the left half of Product register Multiply Algorithm V3 Start Product0 = 0 Product0 = 1 2. Shift the Product register right 1 bit. 32nd repetition? Note: the multiplier is initially Placed in the right ½ of the Product Register No: < 32 repetitions Yes: 32 repetitions cpeg323-08F\Topic3c-323 Done

16. Sign Multiplication • Easiest solution is to • make both positive • remember whether to • complement product when done That is: calculate the sign of the product, convert the operands into positive numbers, leave out the sign bit, run for 31 steps, then fix the result. cpeg323-08F\Topic3c-323

17. Faster Algorithms for Multiplication • Booth’s Algorithm • multiply signed numbers using same hardware as before and save cycles • can handle multiple bits at a time • Using an array of adders • Observation: whether to add or not add a particular shifted multiplicand – a decision can be made all in parallel .. cpeg323-08F\Topic3c-323

18. Divide: Paper & Pencil 1001 Quotient Divisor 1000 1001010 Dividend–1000 10 101 1010–1000 10 Remainder Dividend = Quotient * Divisor + Remainder cpeg323-08F\Topic3c-323

19. Division Algorithm Input: Remainder register is initialized with the dividend; Divisor register is initialized in the left half; Quotient register is initialized with zero. Remainder register <= Subtract the Divisor register from the Remainder register ≥0 <0 Test Remainder register Shift the Quotient register to the left and setting the new rightmost to 1, Remainder register <= Remainder+Divisor Shift the Quotient register to the left and setting the new rightmost to 0 Shift the Divisor register right 1 bit no Repetition n+1 times? yes cpeg323-08F\Topic3c-323

20. Shift Right Divisor 64 bits Quotient Shift Left 64-bit ALU 32 bits Write Remainder Control 64 bits How to do Division ? Note: Dividend is NOT shifting, and Divisor is moving right! How to do division here ? Note: Left ½ of Divisor R is initialized with the divisor, Remainder R is initialized with dividend, Quotient R is initialized with 0. Try to go over the example on P186. cpeg323-08F\Topic3c-323