1 / 28

EE434 ASIC & Digital Systems

EE434 ASIC & Digital Systems. Jacob Murray School of EECS Washington State University jmurray@eecs.wsu.edu. Course Project Part 2. Multicore Processors – State of the art. Single-core. 8-core. Dual-core. GPU. NoC. Larger number of cores Better performance (speed, energy)

tacey
Download Presentation

EE434 ASIC & Digital Systems

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. EE434ASIC & Digital Systems Jacob Murray School of EECS Washington State University jmurray@eecs.wsu.edu

  2. Course ProjectPart 2

  3. Multicore Processors – State of the art Single-core 8-core Dual-core GPU NoC Larger number of cores Better performance (speed, energy) Greater complexity in design and application porting

  4. The Network-on-Chip Paradigm Packet-switched on-chip network • Route packets, not wires – BillDally, 2000 Massive levels of parallelism • Integration of many cores (IPs) Dedicated infrastructure for data transport • Decoupling of functionality from communication NoC infrastructure

  5. Novel Interconnect Paradigms Optical Interconnects Wireless/RF Interconnects Three Dimensional Integration High Bandwidth and Low Energy Dissipation

  6. Proposed Architectures

  7. Data transmission • Packet-based communication • Low memory requirement • Wormhole routing • Deterministic • LCA, e-cube • Virtual channels • enhance channel utilization

  8. Switch architecture

  9. Switch architecture Design This

  10. Mesh Architecture

  11. XY Routing

  12. XY Routing Details Xoffset := Xdest – Xcurrent; Yoffset := Ydest – Ycurrent; if Xoffset > 0 then Channel := X+; endif if Xoffset < 0 then Channel := X-; endif if Xoffset = 0 and Yoffset > 0 then Channel := Y+; endif if Xoffset = 0 and Yoffset < 0 then Channel := Y-; endif if Xoffset = 0 and Yoffset = 0 then Channel := local channel; endif

  13. XY Routing Example

  14. Natural Complex Networks Natural Complex Networks • Brain • Microbes • Social networks Small-World/Exponential graphs • Attacks Scale-free graphs • Random failures

  15. Connecting the Nodes • Small-World graphs: The Watts-Strogatz Model • Often found in nature • Scales well: low average distance Increasing Randomness P=0 P=1 Small-world L:Lo C:Hi Random graph L:Lo C:Lo Regular lattice L:Hi C:Hi • Few High speed long distance Shortcuts: Wireless • Local, shorter links: Wireline

  16. mSWNoC Topology • Power-law based connectivity • Average number of connections is 4 • An upper bound is imposed • One particular switch should not be unrealistically large

  17. Small-World Architecture

  18. TRAIN Algorithm • Suppose we have the interconnection network shown below • Let us make 6 our root node, and build a minimum spanning tree (MST) • Any tree type can be made, you will be given a breadth-first tree 6 2 5 0 1 2 3 7 1 3 0 4 7 4 5 6

  19. TRAIN Continued… • Here, there are three distinct link types • Tree link (solid blue): a direct link in the MST • Shortcut link (dashed red): a wire link not in the MST • Wireless link (dashed green): wireless shortcut not in the MST • There are two link directions • Up: a link traveling up the tree towards the root and ALL shortcuts • Down: a link traveling down the tree away from the root • Can only travel up then down! 6 2 5 7 1 3 0 4

  20. Address-based routing • Address given to each node according to location in MST 6 2 5 7 1 3 0 4

  21. Data route from 3 to 4 • Must take link up to 2. • At node 2 (01000) to 4 (02111): • Best known path to take is 2up to 1. • Must take link from 1 down to 0. • Must take link from 0 down to 4. 6 2 5 7 1 3 0 4

  22. Valid Trees for the Small-World Architecture

  23. Irregular Routing Algorithms • Several limitations of TRAIN routing • Better routing? • MROOTS • Given M virtual channels • Implement M trees, with different roots • Follow a specific tree for a given virtual channel • Additional routing strategies: • LASH, ALASH, etc…

  24. To Do: Undergraduates • Implement the XY Routing block for the Mesh Architecture • Verify the 16 routing blocks route correctly • Choosing several various routers may be sufficient • Implement the TRAIN Routing block for the SW Architecture • Choose one of the four valid trees • Verify the 16 routing blocks route correctly • Choosing several various routers may be sufficient • Synthesize a worst-case routing block • Obtain: Area, Power, Timing • Compare

  25. To Do: Graduates • Implement the XY Routing block for the Mesh Architecture • Verify the 16 routing blocks route correctly • Choosing several various routers may be sufficient • Implement the MROOTS Routing block for the SW Architecture • Choose two of the four valid trees • Verify the 16 routing blocks route correctly • Choosing several various routers may be sufficient • Synthesize a worst-case routing • Obtain: Area, Power, Timing • Compare

  26. No. of I/O Ports MESH SW

  27. Final Outcome

  28. Compare the two architectures • Think about the differences between both architectures. • Advantages? • Disadvantages? • Think about these in terms of ideas we have discussed this semester: layout, area overhead, power, latency, design complexity, test complexity. • Find the average and maximum number of ports • Thoughts about scalability?

More Related