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Digital Baseband Converter. Ying Xiang Xiuzhong Zhang Shanghai Astronomical Observatory China. Background. Analog BBC (Base Band Converter ) 1. In VLBI data acquisition terminal, receiver bands are sent through the IF distributors to the base band converter.

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digital baseband converter

Digital Baseband Converter

Ying Xiang Xiuzhong Zhang

Shanghai Astronomical Observatory

China

background
Background
  • Analog BBC (Base Band Converter)

1. In VLBI data acquisition terminal, receiver bands are sent through the IF distributors to the base band converter.

2. Base band converters down-convert a portion of the receiver band using the so called SSB phasing method.

Analog BBC is complex and expensive.

  • Adopting new digital technology to realize digital BBC (DBBC) may simplify the VLBI data acquisition terminal

-Newest Technology for chip manufacture

-Algorithm

make DBBC approach the needed performance.

why a digital base band converter
Why a Digital Base band Converter?
  • High cost to maintain a high efficiency of band use and very sharp rejection slopes using a switchable bank of analog filters .
  • The use of high-performance filters leads to potential difficulties when temperature and other variations cause the filter properties from antenna to antenna to be mismatched.
  • New disk based recorder is successful in SHAO, bbcs is the next item needing renewal preparing for e-vlbi.
slide4

Advantage of a Digital Base Band Converter

  • Bandwidth selection is highly desirable.
  • Higher overall reliability of the system because of the reduction in components and connections.
  • Lower cost and enhanced band efficiency due to sharper filter shapes are all to be expected with the use of digital filters.
  • Much better band pass matching between the different antennas in the array.
slide5
The digital filter for the VLBI was first developed in KSP, which was developed at the CRL (Communications Research Laboratory), Japan, and begun in 1994.

There’re two kinds of implementations:

slide6

Subband 0

D

S(t)

IF

A/D

D

Subband 1

LO

Subband N-1

D

  • Band pass filters with different center frequency choose different spectral band.
slide7

Subband 0

LO 0

Subband 1

S(t)

IF

A/D

LO 1

Subband N-1

LO

LO N-1

  • Low pass filters and Local oscillator with different tunable frequency choose different spectral band.
  • Digital BBC is realized by the second implementation.
research on dbbc abroad
Research on DBBC Abroad

1、Radioastronomy Institute, Italian National Research Coucil

  • Paper (written by Gino Tuccari)

(1) Development of a Digital Base Band Converter : Basic Elements and Preliminary Results, Proceeding of IVS Symposium – New Technologies in VLBI, Korea, 2002.

slide9

Three parts: 1.5GHz sampler Max108 commercial board

Xilinx VirtexE commercial board

Altera NIOS commercial board for system control

slide10
2、ALMA’s digital BBC (Gianni Comoretto)

Theoretical analysis and simulation for DBBC

  • Papers (written by G. Comoretto)

(1) ALMA memo #305 – A Digital BBC for the ALMA Interferometer

(2) Design of a FIR filter using a FPGA, http://www.arcetri.astro.it/science/Radio/alma/Report_5a_2002.pdf

slide11

Random data generator

Filter Card Under Test

SUM

RAM BUFFER

RAM BUFFER

NCO #1

CORR

NCO #2

125MHz

4GHz

62.5MHz

FIR output

3、Feb. 2002, NRAO (Ray Escoffier etc) gave digital filter card test report which used FPGAs (Field Programmable Gate Array Circuits)

-- Prototype

-- Test report

-- Filter card test signal path

slide12

I

+: LSB

-: USB

delay

In

Digital filter

A/D

Q

90o

Digital filter

sin

cos

DDS

DDC

Layout of DBBC

Note:

Digital filters:spectral band selection and decimation.

90o phase-shift network:Hilbert transformation.

DDS: Direct Digital Frequency Synthesizer

a d sampler
A/DSampler
  • Commercial A/D sampler : Max105

-- maximum sampling: 800Msps

-- 800mv full scale of input

-- LVDS output

-- 6 bits

slide14

Phase truncation

LUT sin/cos

DDS Implementation

Phase Accumulation

12bit

Phase increase

Δθ

NCO

Output

clock

clock

sin

cos

NCO

Output

digital filters

CIC filter

Compensationfilter

Polyphase filter

Digital filters

Digital filters:spectral band selection and decimation.

Implementation: Finite impulse response (FIR).

Decimation Rate:4~16383

Low pass Filtering

Decimation Rate:2~8

-3dB Point Band Efficiency:90%

Pass band Ripple:<0.5dB

Rejection band Attenuation:>40dB

1 8 band polyphase filter
1/8 Band Polyphase Filter
  • Specification:
  • The number of taps: 152
  • Linear phase
  • -3dB Point Band Efficiency:90%
  • Pass band Ripple:<0.5dB
  • Rejection band Attenuation:>40dB
slide17

I

delay

+:LSB

-:USB

Q

Hilbert

90º Phase Shift Network

  • An ideal Hilbert transform provides a phase shift of 90 degrees for positive frequencies and –90 degrees for negative frequencies.
  • A delay match
slide18

Characteristic in Spectral Domain of Hilbert Filter

Figure illustration:

Upper : impulse response

Middle : amplitude

Low : phase

  • Specification of Hilbert filter:

1.Bit length of coefficient: 9

2.-3dB point band efficiency: 98.4%

3.Number of Taps : 99

experimental hardware platform

In

Xilinx

Virtex-II

Out

A/D Sampler

PCI DMA Card

Local Micro-controller

Computer

Experimental Hardware Platform
  • The main task is to design different types of digital filters in FPGAs.
  • PCI DMA card : ADLINK 7300-B
why using fpgas to implement dbbc
Why Using FPGAs to Implement DBBC?

The algorithms to realize digital filter require multiplication and addition in real-time, the unit is called MAC (Multiplication and Accumulation). Three choices of technology exist:

1. ASICs (Application Specific Integrated Circuits)

2. Programmable DSP (Digital Signal Processor) chips

3. FPGAs (Field Programmable Gate Array Circuits)

slide21
ASICs can have multiple dedicated MACs that perform DSP functions in parallel. But they have high cost for low volume production and the inability to make design modifications after production makes them less attractive.
slide22
Programmable DSP chips typically have only one MAC unit that can perform one MAC in less than a clock cycle. DSP processors are flexible, but they might not be fast enough. The reason is that the DSP processor is general purpose and has architecture that constantly requires instructions to be fetched, decoded and executed.
slide23
The FPGA architecture allows multiple MACs and pipelining. Their ability to be modified easily makes them an ideal candidate for DSP functions. The only drawback is the speed, and this can easily be overriden by using computational algorithms suitable for FPGAs.
slide25

DBBC Hardware Platform in SHAO

  • PCI DMA interface card

-- ADLINK 7300-B

  • Max105 A/D sampler

-- 6 bits

-- 800mv full scale

  • Xilinx Virtex-II

-- XC2v1000

-- 100MHz Clock

  • LVDS interface between Virtex-II and A/D sampler
  • Winbond 77E58 for system control
simulation results
Simulation results
  • Simulation in Modelsim and Matlab:
  • The requirement in this design is to get low side band.
  • Simulation_1 shows the result when input is upper side band. Simulation_2 shows the result when input is low side band.

--Simulation_1

--Simulation_2

3. Simulation conclusion