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Communications Baseband

The Communications Baseband Project at the Rochester Institute of Technology is designed to enhance students' hands-on understanding of communication systems. Led by Dr. Joe Delorenzo and his team, this project focuses on modulation techniques including Amplitude, Frequency, and Pulse Code Modulation. Students work through 12 subsystems assessing feasibility and compliance with design objectives, while simulating analog and digital transmissions. The project culminates in a fully functional system demonstrating the design and testing of communication protocols.

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Communications Baseband

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  1. Communications Baseband Project 05500

  2. Members • Advisors: • Dr. Joe Delorenzo • Dr. Eli Saber • Dr. Sohail Dianat • Team Members: • Leland Smith (Team Leader) • Jason Riesbeck (Chief Engineer) • Jonathan Hutton

  3. Introduction • Communications Baseband is a project created by several professors in order to stimulate student’s practical understanding of communication systems. • Sponsor: Rochester Institute of Technology Department of Electrical Engineering

  4. Project Overview • Modulate/Demodulate using Amplitude Modulation, Frequency Modulation, and Pulse Code Modulation • Receive analog or digital transmission approximately a classrooms distance and demodulate • Output original signal to see/hear successful recovery

  5. Team Work Breakdown

  6. Fundamental Design Objectives

  7. Concept Analysis

  8. System Development •Divided into 12 subsystems •Specification developed for each

  9. Feasibility • Assessed at a subsystem level. • Depends on the resources available • To maintain feasibility, subsystems should: • Satisfy design objectives • Economical • Comply with time constraints

  10. FCC Considerations Unlicensed Bands (FCC 15.247.b.4) Antenna gain can be as much as 6dB. All other bands 100mW or less

  11. Audio Subsystem • Block Diagram Input Output

  12. Anti-Aliasing Filter • Specifications: • 0-5V Input • Pass-band 20 kHz • Stop-band 22 kHz • Attenuation 20 dB • Elliptical Filter

  13. Anti-Aliasing Filter Schematic: Plot:

  14. Anti-Aliasing Filter • 6dB Voltage Level = 3dB Power Level = 1.26V • Output =1.26V @ 20.0 kHz • Attenuation =

  15. AM Subassembly • Block Diagrams

  16. AM Modulation • Carrier • 1 MHz Sine Wave • Modulator • Oscillator Input • Audio Input

  17. Carrier Signal • Clock Oscillator • Square Wave • RLC Filter

  18. Carrier Signal

  19. AM Schematic

  20. AM Receiver • AM Receiver • Demodulates Signal • Amplifies the Signal by 18 dB

  21. FM Systems • Complicated to engineer • Could take months in industry Transmitter Receiver

  22. Radio IC’s • A simple and effective solution

  23. Choosing an FM IC

  24. Design Documentation • Schematics • Parts Lists • Specification Documents • Interconnection Control Documents • Test Procedures • Printed Circuit Board

  25. Design Issues • PCB Short

  26. Design Issues • PCB Short • Voltage Regulator Pin-Out

  27. Design Issues • PCB Short • Voltage Regulator Pin-Out • Tuning Capacitor

  28. Design Issues • PCB Short • Voltage Regulator Pin-Out • Tuning Capacitor • Audio Distortion

  29. Design Issues • PCB Short • Voltage Regulator Pin-Out • Tuning Capacitor • Audio Distortion • Tuning Inductor

  30. FM Feasibility

  31. Finished Product FM Transmitter FM Receiver

  32. FSK Systems • Similar to analog FM systems • Also very complicated

  33. FSK Feasibility • Nordic NRF2401 • Transmits data at 1Mbps • 2.4GHz ISM band

  34. FSK Link Analysis • NRF2401 Specification ○ 0dBm output power ○ -80dBm receiver sensitivity • Link Budget Analysis ○ 60dB of attenuation at 10m (with 0dB antenna gain)

  35. Design Documentation • Schematics • Parts Lists • Specification Documents • Interconnection Control Documents • Test Procedures • Printed Circuit Board • FSK Protocol Information

  36. Time Budget

  37. Finished Product

  38. PCM and Control Subassembly • Transmit Side • Conversion of Analog to Digital • Apply Protocol to Digital Data • Manage Memory and Data Flow to FSK Chip • Receive Side • Provide Control to FSK Chip • Receive and Manage FSK Chip Data • Control and Send Data to DAC

  39. Interface Specifications • Rail to rail (0-3.3V) analog signal input • Desire >44 kHz Sample Rate • 1 Mbps transmit rate to FSK chip • Send samples to Digital to Analog Converter at sample rate

  40. Solutions • PICmicro Microcontroller • Analog Devices DAC • 10-bit • No overhead bits • Serial • Up to 20 MHz data rate

  41. Capabilities • PIC offers 10-bit AD • PIC provides I/O ports • USART (Synchronous/Asynchronous Communications), and MSSP (Master Synchronous Serial Port for DAC) • Many I/O Ports for control lines • Provides 1MHz USART • Data storage and management

  42. Chosen Microprocessor • PIC18LF2525 • Low voltage at full speed 3.3V @ 32MHz • Internal oscillator up to 32MHz • External interrupts • MSSP • More robust commands

  43. System Diagram

  44. RX FSK-PIC-DAC Interface • Vref = Vdd

  45. Communications Protocol • PIC must manage data from 10-bit samples to exact 1 Mbps output • USART sends 8-bit words and takes care of data rate • The FSK chip offers several protocol options

  46. IN  PIC  OUT • Known: What goes in must come out – and at the same rate. • Therefore: The rate the PIC can sample at is governed by the FSK communications protocol. • Sampling rate must be some integer number of the outgoing packet rate

  47. Protocol Options

  48. Synchronous with Shockburst Option

  49. Asynchronous Option 1

  50. Asynchronous Option 2

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