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C ern A nd RIOC urrent A mplifier

C ern A nd RIOC urrent A mplifier. An 8 channel ASD front end for the LHCb muon system. Preliminary Design Review February 20 th CERN. Purpose of the Review. See if we are on the right track for submitting a final prototype by middle 2003.

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C ern A nd RIOC urrent A mplifier

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  1. CernAndRIOCurrentAmplifier An 8 channel ASD front end for the LHCb muon system Preliminary Design Review February 20th CERN Werner Riegler CERN, Feb. 20th, 2003

  2. Purpose of the Review • See if we are on the right track for submitting a final prototype by middle 2003. • Get comments from designers who went through the entire chip development and production phase. • Point out critical items or worries. • Find points that we might have overlooked. Werner Riegler CERN, Feb. 20th, 2003

  3. LHCb Muon System 5 muon stations, one in front (M1), 4 behind (M2-M5) the calorimeter A muon trigger requires the coincidence of hits in all 5 stations within the bunchcrossing time of 25ns in a certain spatial window that selects the muon momentum. Granularity 1x2 cm to 10x20cm. Werner Riegler CERN, Feb. 20th, 2003

  4. Detector ‘Standard’ Multi Wire Proportional Chamber Wire pitch 1.5mm, Cathode distance 5mm, 30um wire diameter Wires are connected to form ‘wire pads’, negative signal. Cathodes are segmented to form ‘cathode pads’ positive signal, factor two smaller. Many ‘different’ chamber types Werner Riegler CERN, Feb. 20th, 2003

  5. Many ‘different’ chamber types with different capacitance, grounding, signal flow … The chip has to be tested on ALL chambertypes Werner Riegler CERN, Feb. 20th, 2003

  6. Detector We carefully studied readout and guard trace geometries to minimize crosstalk. Werner Riegler CERN, Feb. 20th, 2003

  7. Detector 2 chamber layers are connected into one frontend. 4 layers of MWPCs are combined into one station. Werner Riegler CERN, Feb. 20th, 2003

  8. Detector and Signal Characteristics • I(t) = I0/(t+1.5ns), • positive (cathode readout) and negative (wire readout) input polarity • Around 100 primary electrons (in two layers) • 30ns average arrival time of last electron • 20s ion tail • 105 gas gain • 1MHz per channel maximum count rate (including safety) • 3.4kV through 1nF … input protection • Detector Capacitance 20-220pF • 50fC average muon signal at the working point (for 10ns peaking time amplifier) • Background signals are factor 2-3 larger. • 125k front end channels. • 8 channels/chip • 1MRad radiation Werner Riegler CERN, Feb. 20th, 2003

  9. Specifications • Positive/negative input polarity • tp=10-15ns in front of the discriminator • Detector capacitance 20-220pF • Input resistance <50 Ohm • Gain of 5mV/fC (delta input) • <50ns average output pulse width • Unipolar signal shaping • Fully differential • Noise <1fC up to 100pF: 5fC cathode pad threshold • <2fC up to 200pF: 10fC wire pad threshold • Baseline Stability Werner Riegler CERN, Feb. 20th, 2003

  10. Baseline Stability The long ion drift (20us) together with the long HV recharge time affects the baseline from a signal for >100us. At 1MHz rate this causes baseline shift of 4fC and baseline fluctuation of 10fC r.m.s. Average Anode Signal (AC coupled) HV loading resistor of 100k together with decoupling capacitor of 680pF gives time constant of 68us. Average Cathode Signal (DC coupled) Ions take >20us to reach the cathode Werner Riegler CERN, Feb. 20th, 2003

  11. Project History • In Jan. 2000 we had no frontend chip that satisfied the needs for the LHCb muon system. • Requirements: tp=10ns, Cdet=10-200pF, Rin<50, +- polarity • Pierre Jarron et. al. (CERN) had just designed a preamp in 0.25m for silicon detectors. • The idea came up to adapt this chip for LHCb. Danielle Moraes (UFRJ, CERN) started this project within her thesis work. • Late 2000, Anatoli Kachtchouk developed the ASDQ++ idea. He adapted the ASDQ (Fermilab COT) to our needs by adding an external transistor to each channel. This solution satisfies our specifications. Drawback: ‘Large’ cost (3.75$/chan. packaged and tested) • We decided to continue the CARIOCA development because of cost reasons and the fact that we have two other 0.25m CMOS chips in the muon system (DIALOG, SYNC)->one production. It also opens the possibility of DIALOG-CARIOCA integration. • The CARIOCA is our preferred solution, ASDQ++ is our fallback. Werner Riegler CERN, Feb. 20th, 2003

  12. CARIOCA Block Diagram Preamp Signal tail cancellation 2x pole/zero, t0=1.5ns, topology from ASDQ Preamp tail cancellation 1x pole/zero, topology from ATLAS MDT Topology from ATLAS MDT LVDS, standard cell topology from ATLAS MDT prototype Werner Riegler CERN, Feb. 20th, 2003

  13. Baseline Restorer The signal AC coupling (wire), the long signal tail (20us) together with high rate (1MHz) result in baseline fluctuations. Solution: 1) Bipolar Shaping -> long dead time, wrong polarity crosstalk 2) Unipolar Shaping - Nonlinear Elements …nonlinear feedback loop: Originally we decided on a time constant of 2us. This was changed to 200ns. Werner Riegler CERN, Feb. 20th, 2003

  14. Prototypes produced so far Werner Riegler CERN, Feb. 20th, 2003

  15. Prototypes produced so far • We had many prototypes because we built up the blocks in a step by step approach and NOT because there were problems. • Up to CARIOCA6 we continuously built up the blocks without encountering problems. • Only on CARIOCA6 some serious problems appeared. • CARIOCA7 was booked already before receiving CARIOCA6, and there was no possibility to cancel it – there was not enough time to fix the problems. • CARIOCA8 was the first submission to really correct a problem. • We see the submission in Q2 /2003 as the final prototype submission. Werner Riegler CERN, Feb. 20th, 2003

  16. People involved up to now(very discontinuous) • Walter Bonivento (CERN, INFN Cagliari) • Anatoli Kachtchouk (CERN, PNPI) • Danielle Moraes (CERN, UFRJ) • Nicolas Pelloux (CERN) • Werner Riegler (CERN) • Delia Rodriguez (CERN) • Burkhard Schmidt (CERN) • Filipe Vinci (CERN) • Up to now we didn’t have a real problem of manpower or a lack of clever people. • We had the big problem of non-continuity of people. • In addition the people involved were ‘newcomers’ to the business of high speed analog fronted ASIC design. • Although we are in frequent contact with the MIC group we were lacking the continuous involvement of a ‘senior’ designer. Werner Riegler CERN, Feb. 20th, 2003

  17. Problems encountered in 2002 • Problems • Offset variations • Shaping: Very large pulse width • ‘Instability‘ (output to input coupling) • Gain difference from specification • Specification changes • We integrated positive and negative preamp into one chip. Werner Riegler CERN, Feb. 20th, 2003

  18. Offsets Variations Werner Riegler CERN, Feb. 20th, 2003

  19. Offsets • CARIOCA6 (March 2002) showed DC offset variations of 48mV r.m.s at the discriminator. • On CARIOCA7 (September 2002) this was reduced to 12mV r.m.s. • On CARIOCA8 (Jan. 2003) we have 4.3mV r.m.s. corresponding to about 1fC. • Our typical threshold is 5fC, cutting on 2 sigma (90% yield) gives 3-7fC threshold. • We decided to use individual thresholds to be safe from the offset problem. Werner Riegler CERN, Feb. 20th, 2003

  20. Shaping Werner Riegler CERN, Feb. 20th, 2003

  21. Shaping, mathematical Mathematical 1/(t+1.5ns) with 2 pole/zero filters 9,2.57ns and 80/40ns, 10ns peaking time amplifier with n=2. ‘Signal tail around 1% at 240ns’, Werner Riegler CERN, Feb. 20th, 2003

  22. Shaping, CARIOCA4 CARIOCA4: preamp+shaper on chamber, Am241, external analog buffer AC coupled Tail cancellation is ‘perfect’, but … Small bump at 70ns, even smaller bump at 280ns, below baseline Werner Riegler CERN, Feb. 20th, 2003

  23. Shaping, CARIOCA5 CARIOCA5: preamp+shaper+discriminator on chamber, shaper to discriminator internally AC coupled, Am241 2.9kV Tail cancellation is ‘perfect’ Werner Riegler CERN, Feb. 20th, 2003

  24. Shaping, CARIOCA6 CARIOCA6: preamp+shaper+BLR+discriminator, fully DC coupled averaged discriminator output signal average pulse width of more than 1us ! Werner Riegler CERN, Feb. 20th, 2003

  25. Shaping, CARIOCA8 • The AC coupling of the analog output of CARIOCA4 and internal AC coupling of the discriminator on CARIOCA5 ‘killed’ the remaining 1% signal tail. • With the full DC coupling of CARIOCA6, this 1% tail causes very long dead time for large background pulses. • For CARIOCA8 we speeded up the BLR to 200ns in order to eliminate this tail (‘nonlinear AC coupling’). Werner Riegler CERN, Feb. 20th, 2003

  26. ASDQ, Am3000V, thr 7fC ASDQ, Am2800V, thr 7fC CARIOCA8, Am3000V, thr 7fC CARIOCA8, Am2800V, thr 7fC Cathode Pad Werner Riegler CERN, Feb. 20th, 2003

  27. ASDQ, Am3300V, thr 7fC ASDQ, Am3200V, thr 7fC CARIOCA8, Am3200V, thr 7fC CARIOCA8, Am3300V, thr 7fC Cathode Pad Werner Riegler CERN, Feb. 20th, 2003

  28. Werner Riegler CERN, Feb. 20th, 2003 Cathode Pad

  29. Shaping • We are close to our goal of about 50ns pulse width. • The detector signal is well defined, therefore signal tail cancellation is well defined 1/(t+1.5ns). • The difficult problem is preamp tail cancellation since the tail is different for positive/negative amplifier and it also changes with the detector capacitance. • For the final submission we have to optimize once more the Shaper and BLR parameters (fine tuning). Werner Riegler CERN, Feb. 20th, 2003

  30. ‘Instability’ Output to Input Coupling Werner Riegler CERN, Feb. 20th, 2003

  31. Instability • For CARIOCA6, all channels went into coherent oscillation for Capacitance >40pF. • Connecting preamp AND dummy preamp to a capacitor made the chip perfectly stable up to 220pF. • We are faced with ground (or substrate) coupling and not with instability due to small phase margin of the chip. • At 220pF, a 20uV ground signal will trigger the 5fC threshold ! • Due to the large detector capacitance our life is very difficult. Werner Riegler CERN, Feb. 20th, 2003

  32. What causes the ‘instability’ • We monitored the analog discriminator input signal on the probe station and connected all 8 inputs to 220pF capacitance -> the board went into oscillation • The ‘oscillation’ signal could be seen on the analog output. • Removing the 100 Ohm LVDS termination didn’t make a difference • Removing the output bond wires from the chip didn’t make a difference • Switching off the LVDS driver decreased the amplitude by about 20%. • Switching off the discriminator (by raising the threshold) made the ‘oscillation’ disappear. • The discriminator switching is mainly responsible for the ‘instability’ • The discriminator switching injects a signal to the preamp through a voltage drop in the supply and ground lines across the wire bonds. Werner Riegler CERN, Feb. 20th, 2003

  33. Cathode pad, CARIOCA8 positive, Am 3300V Top: dummy preamp buffer output (47pF) Middle: averaged dummy preamp output (47pF) Bottom: discriminator Output The discriminator switching causes a signal with 3mV peak -> 4.2 fC !!! Werner Riegler CERN, Feb. 20th, 2003

  34. Symmetric Termination With symmetric termination the chip becomes less sensitive to this effect. Penalty: larger noise, but we can live with it ! Werner Riegler CERN, Feb. 20th, 2003

  35. CARIOCA6 results Measured 2500+45e-/pF symmetric loading and 2500+32e-/pF asymmetric loading threshold at 5 times noise: Cdet thrsym thrasym 0 pF 2 fC 2 fC 50 pF 3.8 fC 3.3 fC 100 pF 5.6 fC 4.6 fC 150 pF 7.4 fC 5.8 fC 200 pF 9.2 fC 7.1 fC 250 pF 11 fC 8.4 fC The difference in terms of minimum threshold is small, and in terms of stability the symmetric loading is much much better ! Werner Riegler CERN, Feb. 20th, 2003

  36. Full size prototype for M2R1 Werner Riegler CERN, Feb. 20th, 2003

  37. Symmetric Termination CERN/RIO M2R1prototype with CARIOCA7 on a board produced in Cagliari. cathode pads: 42-55pF, dummy capactors on board (56pF), Single board Setup is perfectly stable without any ‘special’ grounding or shielding (‘plug and play’). Testbeam with many boards in October. Noise <1fC on the 16 measured channels Idea looks promising and could make our life much much easier. Tests with large capacitance pads will be done later this year. Werner Riegler CERN, Feb. 20th, 2003

  38. CARIOCA7 Chamber test with dummy capacitance(50pF cathode pads, 7fC threshold) Result meets specification Werner Riegler CERN, Feb. 20th, 2003

  39. ‘Instability’ • Using symmetric termination we can reduce common mode noise. • We identified the discriminator switching as the source for the ‘instability’. • For the next submission we will use massive ‘on chip’ filtering of the discriminator power and ground lines in order to reduce this effect. Werner Riegler CERN, Feb. 20th, 2003

  40. Gain difference from specification • On CARIOCA6 and CARIOCA7 the positive amplifier showed very strong nonlinearity at small charges. • The reason was a too small ‘feedback current’ that put the amplifier on the very edge of the linear range. This was solved by simply increasing this current from 6 to 18uA. Werner Riegler CERN, Feb. 20th, 2003

  41. Conclusion • The LHCb muon system uses a large variety of detector geometries. • In addition the specifications for the frontend performance are very tight (large Cdet, High Speed, High Rate etc.). • With CAIOCA8 we have a prototype that seems not too far from our final goal. • The final prototype has to be submitted in June 2003. Werner Riegler CERN, Feb. 20th, 2003

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