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Lecture 6

Lecture 6. Machine Code: How the CPU is programmed. Registers. AX (16 bits, old 8086 size). Intel: General Purpose, e.g. Pentium EAX register There are also EBX, ECX, EDX registers, as above, all 32 bits

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Lecture 6

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  1. Lecture 6 Machine Code: How the CPU is programmed

  2. Registers AX (16 bits, old 8086 size) • Intel: General Purpose, e.g. Pentium EAX register • There are also EBX, ECX, EDX registers, as above, all 32 bits • Intel processors are backwards compatible – so Pentiums can run programs which only use the old 8086 AX, BX .. sub-registers. Things like this are called Legacy issues. • Intel: General purpose • EDI, ESI, EBP, ESP – all 32 bits and all with 8086 sub parts (DI,SI,BP,SP). The first 3 of these are generally used to set up relative or indexed addresses. The Stack Pointer ESP or SP is quite special and we will look at this separately. AH AL (AH and AL are usable 8 bit sub-divisions of AX) EAX (32 bits, full Pentium size)

  3. Registers (2) • Intel: Control registers • PC Program counter – address of the next instruction (sometimes called IP) • SR Status register (each bit records some status info, eg for overflow). Sometimes called Condition Codes CC register. • MAR and MBR buffer registers for address or data used by the adress or datat bus. • IR buffer register for the current instruction • Intel: Segment registers • CS, DS, SS segment addresses for code, data, stack • ES, FS, GS other segment registers • Other processors from other manufactures have different register arrangements, e.g. the Power PC (IBM, Apple) has simply 32 general purpose 32 bit registers (along with the same kind of PC, SP and control registers etc)

  4. Intel’s logical addressing system • Intel has always divided memory into logical segments. This helps with organizing memory – different segments can be for different things e.g. machine code instructions can go in a code segment, data can go in data segments, the stack can use a stack segment and so on (and extra segments can be set by the programmer). So, for logical purposes, Intel addresses get divided into two parts a segment address and an offset address within the segment: e.g. 0151: 6F79 • There are segment registers (CS, DS etc) to keep track of the current segments being used. • A physical 32 bit address still has to be presented to the Address bus, so there is some translation to be done between Intel’s logical Segment:Offset address and a straight 32 bit physical address. • NB Not all manufactures use the segmentation idea – e.g. in the Power PC all address are just simple 32 bit addresses – this gives flexibility – there is no pre-organisation of memory Offset from the start of the segment Address of the segment

  5. Addressing modes • All CPU’s provide a range of different addressing modes. These are flexible and convenient ways which allow programmers to access the correct data for their programs. Without these different addressing modes, programming would be hard (maybe sometimes impossible) and very inefficient. Knowing all about a particular CPU’s many addressing modes in detail is for fairly advanced machine code programmers. But all CPU’s share a few very similar basic addressing modes which any computer engineer should be reasonably familiar with, as follows: • Register addressing e.g. MOV AX, BX Here the CPU doesn’t make any reference to memory but just works with its own registers • Immediate addressing e.g. MOV DX, 45 Here the data needed is in the instruction itself (and so is in the Code Segment) and so the CPU again does not have to fetch anything from data memory (since it has already fetched the instruction). • Direct or Absolute Addressing e.g. MOV BX, [1001] Here the address of the data in memory (in the Data Segment) is given in the instruction, so in this example the data at DS:1001 is copied to BX. • Indirect addressing e.g. MOV AX, [BX] Here the address of the data is in another register. So here the CPU takes the value in BX, and uses it as an offset address in the Data Segment from which to copy data into AX.

  6. A simple example

  7. Stacks • Provide temporary storage for things. • In our simple examples, just the return addresses for Sub-Routines and Interrupt Service Routines. • But in modern programming stacks are used very extensively – for example when a new object is created in Java (or in other OOP languages), all the variables and other information for the object is pushed onto a stack and accessed from there. The stack memory used can be re-used once the object is not needed any more. • Are last in first out queues (LIFO) • PUSH places bytes (2 bytes for 8086 or larger words depending on the computer) • POP retrieves bytes (2 for 8086) from the stack • Grow to lower memory • Have a stack pointer (SP) for the address of the last byte added with a PUSH (and also the next byte that would be removed with a POP) • PUSH decrements SP by 1, then stores the bytes identified in the PUSH instruction • POP reads the bytes from the stack and then increments SP by 1 • Remember the SP points to the bottom of the stack

  8. Sub-routine call and return • This example from Coope et al’s book uses three levels on the stack - each time a sub-routine is called, the address of the instruction to come back to is pushed onto the stack. This is called the Return Address (RA).Address Label Assembler code comments // Code for the ‘main’ program • CS:0500 etc some instruction before calling the PRINT_TAX sub-routine CS:0503 CALL PRINT_TAX pushes RA (0506) onto stack, then sets IP to the to the first instruction of PRINT_TAX CS:0506 CARRY_ON etc the next instructions after the call // Code for the PRINT_TAX subroutineCS:0600 PRINT_TAX CALL CALC_TAX pushes RA (0603), then sets IP to the to the first instruction of CALC_TAX. CS:0603 CALL PRINT pushes RA (0606), then sets IP to the to the first instruction of PRINT, a standard O/S sub- routine. Note that PRINT will itself end with a RET, and so will POP the 0606 address into IP, coming back to the next instruction, which is the RET of PRINT_TAXCS:0606 RET pops a new value for IP, to return from PRINT_TAX // Code for the CALC_TAX subroutine CS:0700 CALC_TAX MOV CX,175CS:0706 MUL CXCS:0709 RET

  9. Some machine code examples • Example of an unconditional branch instruction (BRA) start: CALL read_user_input CALL calc_next_position CALL redraw_screen BRA start • Example of a conditional branch (BNE. In this example, TABLE is an address in memory, in the DATA segment). LEA means Load the Effective Address. LEA BX,TABLE // copy the address of TABLE into BX MOV CX,10 // use CX for a counter MOV AX,0 // use AX for a running total loop: ADD AX,[BX] ADD BX,2 // move address on to next part of table DEC CX CMP CX,0 BNE loop

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