Chapter Goals

Chapter Goals • Describe CPU instruction and execution cycles • Explain how primitive CPS instructions are combined to form complex processing operations • Describe key CPU design features, including instruction format, word size, and clock rate • Describe the function of general-purpose and special-purpose registers Systems Architecture, Fifth Edition

Chapter Goals (continued) • Compare and contrast CISC and RISC CPUs • Describe the principles and limitations of semiconductor-based microprocessors Systems Architecture, Fifth Edition

Systems Architecture, Fifth Edition

CPU Operation • Control unit • Moves data and instructions between main memory and registers • Arithmetic logic unit (ALU) • Performs computation and comparison operations • Set of registers • Storage locations that hold inputs and outputs for the ALU Systems Architecture, Fifth Edition

Actions Performed by CPU Systems Architecture, Fifth Edition

Instructions and Instruction Sets • Instruction • Lowest-level command • A bit string, logically divided into components (op code and operands) • Three types (data movement, data transformation, sequence control) • Instruction sets • Collection of instructions that a CPU can process Systems Architecture, Fifth Edition

Data Movement Instructions • Copy data (MOVE) among registers, primary storage, secondary storage, and I/O devices Systems Architecture, Fifth Edition

Data Transformations • Implement simple Boolean operations (NOT, AND, OR, and XOR) • Implement addition (ADD) • Implement bit manipulation (SHIFT) • Logical shift • Arithmetic shift Systems Architecture, Fifth Edition

Sequence Control Operations • Control the next instruction to be fetched or executed • Operations • Unconditional branch • Conditional branch • Halt Systems Architecture, Fifth Edition

Complex Processing Operations • Implemented by appropriate sequences of primitive instructions • Represent combinations of primitive processing operations • Represent a tradeoff between CPU complexity and • Programming simplicity • Program execution speed Systems Architecture, Fifth Edition

Instruction Set Extensions • Additional instructions required when new data types are added • Some include instructions that combine data transformation with data movement Systems Architecture, Fifth Edition

Instruction Format • Template describing op code position and length, and position, type, and length of each operand • Vary among CPUs (op code size, meaning of specific op code values, data types used as operands, length and coding format of each type of operand) • Most CPUs support multiple instructional formats Systems Architecture, Fifth Edition

Instruction Length Systems Architecture, Fifth Edition

Reduced Instruction Set Computing (RISC) • Uses fixed length instructions, short instruction length, large number of general-purpose registers • Generally avoids complex instructions, especially those that combine data movement and data transformation • Simpler but less efficient than CISC (Complex Instruction Set Computing) Systems Architecture, Fifth Edition

Clock Rate • Number of instructions and execution cycles potentially available in a fixed time interval • Typically measured in thousands of MHz(1000 MHz = 1 GHz) • Rate of actual or average instruction execution is measured in MIPS or MFLOPS • CPU cycle time – inverse of clock rate • Wait state Systems Architecture, Fifth Edition

CPU Registers • Primary roles • Hold data for currently executing program that is needed quickly or frequently (general-purpose registers) • Store information about currently executing program and about status of CPU (special-purpose registers) Systems Architecture, Fifth Edition

General-Purpose Registers • Hold intermediate results and frequently needed data items • Used only by currently executing program • Implemented within the CPU; contents can be read or written quickly • Increasing their number usually decreases program execution time to a point Systems Architecture, Fifth Edition

Special-Purpose Registers • Track processor and program status • Types • Instruction register • Instruction pointer • Program status word (PSW) • Stores results of comparison operation • Controls conditional branch execution • Indicates actual or potential error conditions Systems Architecture, Fifth Edition

Word Size • Number of bits a CPU can process simultaneously • Increasing it usually increases CPU efficiency, up to a point • Other computer components should match or exceed it for optimal performance • Implications for system bus design and physical implementation of memory Systems Architecture, Fifth Edition

Enhancing Processor Performance Systems Architecture, Fifth Edition

Range of Possible Approaches for Multiprocessing • Duplicate circuitry for some or all processing stages within a single CPU • Duplicate CPUs implemented as separate microprocessors sharing main memory and a single system bus • Duplicate CPUs on a single microprocessor that also contains main memory caches and a special bus to interconnect the CPUs Systems Architecture, Fifth Edition

The Physical CPU • Electrical device implemented as silicon-based microprocessor • Contains millions of switches, which perform basic processing functions • Physical implementation of switches and circuits Systems Architecture, Fifth Edition

Switches and Gates • Basic building blocks of computer processing circuits • Electronic switches • Control electrical current flow in a circuit • Implemented as transistors • Gates • An interconnection of switches • A circuit that can perform a processing function on an individual binary electrical signal, or bit Systems Architecture, Fifth Edition

Electrical Properties Systems Architecture, Fifth Edition

Processor Fabrication • Performance and reliability of processors has increased with improvements in materials and fabrication techniques • Transistors and integrated circuits (ICs) • Microchips and microprocessors • First microprocessor (1971) – 2,300 transistor • Current memory chip – 300 million transistors Systems Architecture, Fifth Edition

Microprocessors • Use small circuit size, low-resistance materials, and heat dissipation to ensure fast and reliable operation • Fabricated using expensive processes based on ultraviolet or laser etching and chemical deposition Systems Architecture, Fifth Edition

Current Technology Capabilities and Limitations • Moore’s Law • Rate of increase in transistor density on microchips doubles every 18-24 months with no increase in unit cost • Rock’s Law • Cost of fabrication facilities for chip generation doubles every four years • Increased packing density • Electrical resistance Systems Architecture, Fifth Edition

Future Trends • Semiconductors are approaching fundamental physical size limits • Technologies that may improve performance beyond semiconductor limitations • Optical processing • Hybrid optical-electrical processing • Quantum processing Systems Architecture, Fifth Edition

Optical Processing • Could eliminate interconnection and simplify fabrication problems; photon pathways can cross without interfering with one another • Eliminating wires would improve fabrication cost and reliability • Not enough economic incentive to be a reality yet Systems Architecture, Fifth Edition

Electro-Optical Processing • Devices provide interface between semiconductor and purely optical memory and storage devices • Gallium arsenide (both optical and electrical properties) • Silicon-based semiconductor devices (encode data in externally generated laser light) Systems Architecture, Fifth Edition

Quantum Processing • Uses quantum states to simultaneously encode two values per bit (qubit) • Uses quantum processing devices to perform computations • Theoretically well-suited to solving problems that require massive amounts of computation Systems Architecture, Fifth Edition

Summary • CPU operation • Instruction set and format • Clock rate • Registers • Word size • Physical implementation • Future trends Systems Architecture, Fifth Edition

Chapter Goals - PowerPoint PPT Presentation

Presentation Transcript