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Innovative Silicon Drift Detectors for SIDDHARTA-2 Upgrade

This study focuses on the new development of Silicon Drift Detectors (SDDs) for the SIDDHARTA-2 experiment upgrade. It covers the features, integration of input FET, anode technologies, and the performance improvements of the new SDDs. The text highlights the advantages of the proposed technological approach, including simpler processes, lower production costs, and faster production times. It also introduces the Cube preamplifier for high-performance X-ray spectroscopy. The study presents the new layouts and advancements in SDD technology designed by the Politecnico di Milano and FBK collaboration, aiming to enhance the capabilities of the SIDDHARTA-2 setup.

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Innovative Silicon Drift Detectors for SIDDHARTA-2 Upgrade

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  1. New Development of Silicon Drift Detectors for the SIDDHARTA-2 experiment upgrade Carlo Fiorini, Riccardo Quaglia Politecnico di Milano, Dipartimento di Elettronica, Informazione e Bioingegneria, Milano, Italy. INFN, Sezione di Milano, Milano, Italy.

  2. Outline • The Silicon Drift Detectors (SDDs) in SIDDHARTA-1 • New development of SDDs for SIDDHARTA-2 upgrade • Present and future work

  3. SIDDHARTA SIlicon Drift Detector for Hadronic Atom Research by Timing Applications • LNF- INFN, Frascati, Italy • SMI- ÖAW, Vienna, Austria • IFIN – HH, Bucharest, Romania • Politecnico, Milano, Italy • MPE, Garching, Germany • PNSensors, Munich, Germany • RIKEN, Japan • Univ. Tokyo, Japan • Victoria Univ., Canada

  4. Anodes Integration of the input FET on the detector to: - reduce of the parasitic capacitances of the connections between detector and electronics - improvement of the capacitive matching between detector gate capacitances (CdetCgate) • Features: • optimized geometry for X-ray Spectroscopy • low-noise, high-resolution Ionizing particle Rectifying electrodes • The electrons are collected by the small anode, • characterised by a low output capacitance, independent from the active area • The drift time can be used to retrieve the position of interaction Anode The Silicon Drift Detector (SDD)

  5. SDD board detector +readout module readout board with ASIC 3 SDD (1cm2 each) with on-chip JFET and feedback cap

  6. Silicon Drift Detector - SDD 1Chip : 1 cm2

  7. 1 cm2 x 144 SDDs

  8. What have we learned about the SDDs of SIDDHARTA-1? • SDDs are a valuable X-ray spectroscopy detector for exotic atoms measurements • but: • latch-up of JFET integrated in the SDD during beam injection • very fine tuning of bias of individual SDD was required • dead-area of the detection module may be further minimized • low-energy detection (<3keV) limited because of technical issues (electronics, thresholds, pick-up noise, …). • …but no intrinsic SDD limitations (>200eV) • ….. • (our friends in Frascati may have learned much more than us….)

  9. The SIDDHARTA-2 setup upgrade • new target design • new SDD arrangement • vacuum chamber • more cooling power • improved trigger scheme • shielding and anti-coincidence (veto) • New SDDs – Milano – 200 cm2 9

  10. New development of SDDs by Politecnico & FBK • Started in 2011 within a project supported by ESA • Considered very suitable for the upgrade of the Siddharta-2 apparatus, with preliminary evaluation on prototypes in 2012/2013 • Key features of the proposed technological approach: • process of SDD detectors WITHOUT JFET integrated on the SDD itself (as used on current SIDDHARTA apparatus). • advantages: • - simplicity • - much lower production costs (much less techn. steps) • - faster production times (3-4 months vs. one year) • - much lower dependence of settings/performances on bias voltages than with the present detectors • - less sensitivity to latch-up during beam injection • SDD readout based on a new charge preamplifier “Cube” (recently developed at Politecnico di Milano): • - allows high performances in X-ray spectroscopy still using ‘conventional’ SDD technology (W/O integrated JFET)

  11. Present layouts of SDDs developed in the Polimi-FBK collaboration Array: 9 SDDs (8 x 8 mm2 each) 8 x 8 mm2 single SDD 26mm 12 x 12 mm single SDD • FBK production: • 4’’ wafer • 6’’ wafer upgrade just finished

  12. Front-end readout strategy radiation entrance window • JFET integrated on the SDD SDD • lowest total anode capacitance • limited JFET performances (gm, 1/f) • sophisticated SDD+JFET technology Now in Siddharta cooler CUBE • external CUBE preamplifier • (MOSFET input transistor) Proposed for Siddharta-2 • larger total anode capacitance • better FET performances • standard SDD technology

  13. CUBE: A full CMOS preamplifier can replace the single JFET+Cf+reset <1mm3 Leakage and photons reset 30 ns 55Fe signal (SDD) CUBE SDD

  14. Best performances of new SDD technology and CUBE preamplifier 55Fe spectrum 123.0 eV FWHM • SDD characteristics: • Area = 10mm2 • T= -40°C (ENC= 3.7 e- rms) 1.0 ms shaping time (optimum) 250ns shaping time 126.4eV FWHM best resolution ever obtained with a SDD (even with integrated JFET) at this short shaping time (ENC= 5.0 e- rms)

  15. Stability of the X-ray spectroscopy spectrum with SDD bias

  16. Set-up for testing SDDs: Vacuum Chamber Cryostat cooling down to 50 K Vacuum Chamber Connector to output Special 55Fe source for vacuum application mounted here Connector for bias and output SDD: 8x8 mm2

  17. Stability tests (in Milano, other tests on-going in Frascati) 72 hours FWHM= 126.8eV square SDD: 64 mm2 meas. time: 72 hours T= 100 K Rate: 1.1 kcps Vacuum chamber set-up.

  18. Monolithic array of 3x3 SDDs: an ideal detector for Siddharta-2 upgrade 26mm • 55Fe spectra • T=-20°C 1mm dead space on each side: 85% active area 9 holes for bondings CUBE preamplifier Detector module connector Ceramic carrier

  19. Upgrade of Siddharta-2 spectrometer based on: • new SDDs development • CUBE and ASICs readout • low dead-area detection module design • Few numbers: • 200cm2 of SDDs arrays • 36 SDDs monolithic arrays • 324 readout channels (drawings courtesy of SMI-ÖAW team)

  20. ASIC to readout the SDD arrays • 27 channels • Shaper filter Semi-Gaussian 7th order complex poles. • Peaking Time 2, 3, 4 or 6µs • 3 Gain: 10k, 20k, 30k e-; • SPI 160 bits; • Multiplexer 27 to 1 • MUX clock 10 MHz • Digital transfer standard LVDS ASIC From/To preamplifiers (Input signals, Reset) DAQ

  21. Present and future work • Experimentation of single SDD (8x8mm2) almost completed • (resolution, stability, linearity….) • Experimentation of 3x3 SDDs array on the way: • mounting and bonding optimization, yield • test at low temperatures (100K) • qualification as for the single SDD (Milano, Frascati) • Design of a readout ASIC for the new SDD arrays • Revision/design of the DAQ system • Revision of components (detector layout, hybrids, module, …) for the SIDDHARTA-2 upgrade and production (depending on financing and support to man-power)

  22. The new SDD development collaboration Politecnico di Milano and INFN, Milano, Italy C. Fiorini, R. Quaglia, P. Busca, R. Peloso, M. Occhipinti, L. Bombelli, A.Geraci Fondazione Bruno Kessler - FBK, Trento, Italy P. Bellutti, M. Boscardin, F. Ficorella, G. Giacomini, A. Picciotto, C. Piemonte, N. Zorzi LNF - INFN, Frascati, Italy M. Bazzi, M. Iliescu, F. Sirghi, C. Curceanu, ….

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