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Towards Next generation INCODE

Embedded System Group @ CSE IIT Delhi . Chronology of INCODE. Early 90's: CSE started using FPGA as a part of student projects.1995: A regular laboratory curricula was introduced.1999: INCODE was developed.2001: To popularize FPGA design among other engineering colleges in India the tech

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Towards Next generation INCODE

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    1. Towards Next generation INCODE Embedded System Group IIT Delhi

    2. Embedded System Group @ CSE IIT Delhi Chronology of INCODE Early 90’s: CSE started using FPGA as a part of student projects. 1995: A regular laboratory curricula was introduced. 1999: INCODE was developed. 2001: To popularize FPGA design among other engineering colleges in India the technology was transferred to M/S VPL InfoTech and consultant Ltd.

    3. Embedded System Group @ CSE IIT Delhi Motivation behind INCODE development A versatile kit which can be used for laboratory experiments. A Low cost board which can be used as teaching aids. Incorporate latest techniques and methodologies in the curriculum.

    4. Embedded System Group @ CSE IIT Delhi The INCODE Hardware

    5. Embedded System Group @ CSE IIT Delhi The INCODE Software

    6. Embedded System Group @ CSE IIT Delhi A closer look on the Design.

    7. Embedded System Group @ CSE IIT Delhi Two Major features… Downloading the bit file to the targeted FGPA Foremost task to be performed by the tool is to transfer the design to the FPGA, which is achieved by downloading the bit file. Hardware Software co-design environment. Providing ways for hardware software interaction.

    8. Embedded System Group @ CSE IIT Delhi Downloading the Design on FPGA Mode of download Slave Serial mode FPGA is slave and bit file is serially transferred. Master Serial mode FPGA is Master and bit file is serially transferred. Select Map Mode Bit file is transferred one byte at a time. Boundary Scan mode Through JTAG cable

    9. Embedded System Group @ CSE IIT Delhi Slave serial configuration mode flow chart

    10. Embedded System Group @ CSE IIT Delhi Hardware software Co-Design Data can be transferred from the PC to the Hardware design in the FPGA. Software functions can be downloaded and run on the 8051 microcontroller.

    11. Embedded System Group @ CSE IIT Delhi Why New board design? 4000 family FPGA production and support has been discontinued. Bigger designs can not be implemented. Multiplatform Tool. To add more features to the tool and keep the pace with latest technology.

    12. Embedded System Group @ CSE IIT Delhi Next version Enhancements were continuously done by adding the library components and case studies. To incorporate the bigger designs the hardware was required to upgraded. New board with Virtex-E family FPGA was designed in 2003.

    13. Embedded System Group @ CSE IIT Delhi The boards together

    14. Embedded System Group @ CSE IIT Delhi Problems … The working version of the software's were misplaced. The Virtex-E board design did not considered the fact that it is a low voltage design.

    15. Embedded System Group @ CSE IIT Delhi Solutions … The Firmware for 8051 was re-written. Code was written in C using Keil cross compiler. Is an application running over on RTOS (RTX51 Tiny). The Hardware was interfaced with a ARM7 based microcontroller LPC2129 for configuration. Testing is in progress.

    16. Embedded System Group @ CSE IIT Delhi Requirements for new board Advance FPGA Advance microcontroller Faster communication channel Better Co-design environment

    17. Embedded System Group @ CSE IIT Delhi Few compressions ….

    18. Embedded System Group @ CSE IIT Delhi Proposed Block diagram for new board design

    19. Embedded System Group @ CSE IIT Delhi Configuration: Select Map Mode

    20. Embedded System Group @ CSE IIT Delhi LPC2294: ARM7 based 32-bit Microcontroller 32-bit ARM7 microcontroller in a 144 pin package. 16 KB on-chip static RAM and 256KB on-chip Flash program memory. In-system programming. 112 general purpose I/O pins. Low voltage operations. On-chip peripherals like 10-bit ADC, 2 serial ports, CAN interfaces.

    21. Embedded System Group @ CSE IIT Delhi Towards next generation INCODE…. Goals Enhanced features. Multiplatform Tool. Achievements Interfaced the Virtex-E with ARM7 based LPC2129 microcontroller. Written Code to configure the FPGA in slave serial mode. Component study has been done. To be done Freeze the specifications. Detailed design. Documentation (Manuals, Website).

    22. Embedded System Group @ CSE IIT Delhi

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