ADVANCE Multi-simulation Concepts

1. ADVANCEMulti-simulation Concepts John Colley 10th November 2011 Southampton

2. Introduction • Motivation • Discrete Event Simulation Principles • Single-thread/Multi-thread Implementations • Co/Multi-simulation Principles • Two Simulators • More than Two Simulators • Continuous Simulation Principles • Hybrid Continuous/Discrete Multi-simulation • Summary

3. Discrete Event Simulation: Motivation • Dominant Verification Technology for Synchronous Digital Hardware and Systems on Chip • $300 million per year Market • Mature Tools (30 years of development) • High Price Tools ($30k per seat + maintenance) • Single Kernel, Multi-Language Tools for Model Re-use • VHDL • SystemVerilog • SystemC (C++) • C

4. Discrete Event Simulation COMPONENT VIEW Components: A, B, C, D (processes) Connections: C1, C2 (unidirectional) Ports: IN OUT SIMULATOR API GetValue(port) HasChanged(port) SetValue(OUT port, val, delay) ScheduleEval(component, delay) A B C1 D C C2

5. The Two-list Simulation Algorithm t = n A B C1 update list D t = 0 C C2 evaluation list

6. The Two-list Simulation Algorithm t = n A B C1 Why not just have a single, time-ordered list? update list D t = 0 C C2 evaluation list

7. Time Zero Initialisation: Evaluate all Components A B C1 update list D t = 0 C C2 A B C D evaluation list

8. Component evaluations call SetValue, ScheduleEval t = 50 EC A B t = 30 ED C1 t = 30 C2 update list t = 20 C1 D t = 0 C C2 evaluation list

9. Component evaluations call SetValue, ScheduleEval t = 50 EC C: future eval A B t = 30 ED C1 D: future eval t = 30 C2 update list C: C2 new val t = 20 C1 A: C1 new val D t = 0 C C2 evaluation list

10. Global Time is Advanced to t = 20 t = 50 EC A B t = 30 ED C1 t = 30 C2 update list t = 20 C1 D t = 0 C C2 evaluation list

11. Add to eval list each component on C1 fanout t = 50 EC A B t = 30 ED C1 t = 30 C2 update list t = 20 C1 D t = 0 C C2 B D evaluation list

12. B calls ScheduleEval with delay 40 t = 50 EC t = 60 EB A B t = 30 ED C1 t = 30 C2 update list t = 20 C1 D C C2 B D evaluation list

13. Time advances to t = 30: two updates t = 50 EC t = 60 EB A B t = 30 ED C1 t = 30 C2 update list t = 20 C1 D C C2 evaluation list

14. Time advances to t = 30: two updates, oneeval A B C1 t = 60 EB update list t = 50 EC t = 30 ED D t = 30 C2 C C2 D evaluation list

15. Simple Algorithm, Complex Implementation forPerformance A B C1 t = 60 EB update list t = 50 EC t = 30 ED D t = 30 C2 C C2 evaluation list

16. Simple Algorithm, Complex Implementation forPerformance A B C1 Why not just have a single, time-ordered list? RACE t = 60 EB update list t = 50 EC t = 30 ED D t = 30 C2 C C2 evaluation list

17. Simulating Models without Discrete Delays –Unit Delay A B C1 Each evaluate/update cycle advances time by one tick EB C1 D update list C C2 evaluation list

18. The Simulation Testbench B A C1 Primary outputs Primary inputs D C C2

19. The Simulation Testbench B A C1 • In principle, just another component using the API • In practice, a complex model of the design environment: • Constrained Random Test Generation • Assertion Checking • Functional Coverage Metrics Primary outputs Primary inputs D C C2

20. Discrete Event Simulation Languages: Hierarchy B A C1 D C C2

21. Discrete Event Simulation Languages: Hierarchy B A C1 D C C2 Hierarchy is flattened for simulation

22. Discrete Event Simulation Languages: Function • There must be an Entry Point to implement the EvalAPI call • Evalcallmust execute to completion • Method call • Actor • Languages with Embedded Wait • Evalcall must resume at the Wait Point • Implement as Finite State Machine • Stored Current State represents the next Entry Point

23. A Concurrent Simulator Implementation? t = n A B C1 update list D t = 0 C C2 evaluation list

24. A Concurrent Simulator Implementation t = n A B C1 update list Atomic Insertion D t = 0 C C2 A B C D evaluation list EVAL Components in Parallel

25. A Concurrent Simulator Implementation t = n A B C1 update list Amdahl’s Law Revisited for Single Chip Systems Jo-Ann M. Paul and Brett H. Meyer, 2006 Atomic Insertion D t = 0 C C2 A B C D evaluation list EVAL Components in Parallel

26. Event-Driven vs Process-Driven • Event-Driven • Single core, single process • Process-Driven • Threads • OpenMP • Portable • Optimised for multi-core • Python Generators (coroutines) • Single core only (SimPy)

27. What if Component D does not have a native implementation? t = n A B C1 update list C3 D t = 0 C C2 A B C D evaluation list

28. Component D is simulated with a different Simulator:Co-Simulation t = n A B C1 update list C3 D External Model t = 0 C C2 A B C D evaluation list

29. Master/Slave Co-Simulation • Master Simulator • Master Event Queue • Design Topology • Components • Connectors • Initiates the Slave and establishes Inter-Process Communication A B C1 C3 D External Model • Slave Simulator • Slave Event Queue • Slave Component C C2

30. Master/Slave Co-Simulation • Co-Simulation • Initialise Master Simulator • Initialise Slave Simulator • Get time Ts of next event from Slave • Run Master until • Time = Ts OR • D sees change on C1 or C2 • Get time Tm of next event from Master • Tell Slave to run until • Time = Tm • B sees change on C3 A B C1 C3 D External Model C C2

31. What if B is represented by a 3rd Simulator? • Master Simulator • Initialise Master Simulator • Initialise Slave Simulator • Get time Ts of next event from Slave • Run Master until • Time = Ts OR • D sees change on C1 or C2 • Get time Tm of next event from Master • Tell Slave to run until • Time = Tm • B sees change on C3 A B ExternalModel C1 C3 D External Model C C2

32. What if B is represented by a 3rd Simulator? • Master Simulator • Initialise Master Simulator • Initialise Slave Simulator • Get time Ts of next event from Slave • Run Master until • Time = Ts OR • D sees change on C1 or C2 • Get time Tm of next event from Master • Tell Slave to run until • Time = Tm • B sees change on C3 A B ExternalModel C1 Simulators run in Lock-Step C3 D External Model C C2

33. Two Simulators, Slave Evaluates much more slowly than Master and Slave can Backtrack • Co-Simulation • Initialise Master Simulator • Initialise Slave Simulator • Run Slave • Run Master until D sees a change on C1 or C2 at time Tc • If Slave time Ts < Tc • Continue running Slave until Tc • Else • Slave backtracks to Tc • Slave accepts new input value A B C1 C3 D External Model C C2

34. Continuous v Discrete Simulation Continuous Discrete Assignment-based always @ (posedgeclk) begin x <= x + 1 y <= x - 1 end • Equation-based model cont01 Real x, y, z; equation x + y + z = 5.000; der(y) = x + 1.365; y = der(z) – 1.875; end cont01;

35. Hybrid Modeling • Continuous-time + Discrete-time Modeling • Modelica “when” model t03 Real x, y, z; equation x + y + z = 5; when sample(0, 1) then x = x + 1; y = delay(x – 1, 20); end when; end t03;

36. What if B is represented by a Continuous Simulator? • Multi-Simulation • A, C in Master multi-sim environment • B in Continuous Simulator • Modelica • Simulink • D in 3rd party Discrete Simulator • IN/OUT interfaces to B must be Discrete • Modelica when A B External Model C1 C3 D External Model C C2

37. Multi-sim Architecture A ADVANCE Rodin Platform ProB Multi-Simulation Core 3rd Party sim 3rd Party sim . . .

38. Summary • Discrete Event Simulation • Two-List Algorithm for Deterministic Execution • “Event-driven” or “Process-driven” • Hardware/Software • Continuous Simulation • Modelica, Matlab/Simulink • Co-Simulation/Multi-Simulation • Optimisations for 2 Simulators • More than 2 Simulators must run in Lock-Step • Hybrid Continous/Discrete Simulation • Discrete Interfaces