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n-XYTER Hybrid Developments. Christian J. Schmidt et al., GSI Darmstadt. JINR, Dubna, Oct. 15 th 2008. n-XYTER, current workhorse chip for prototyping. workhorse readout chip for detector prototyping architectural example front-end for DAQ development (self triggered, data driven)

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n xyter hybrid developments

n-XYTER HybridDevelopments

Christian J. Schmidt et al.,

GSI Darmstadt

JINR, Dubna, Oct. 15th 2008

n xyter current workhorse chip for prototyping
n-XYTER, current workhorse chip for prototyping
  • workhorse readout chip for detector prototyping
  • architectural example front-end for DAQ development (self triggered, data driven)
  • sample ASIC for technological front-end electronics hybrid developments
    • bonding technology, circuit board technology
    • thermal management, active cooling concepts
    • power management (integraly high currents, low voltage, high B-fields, high rad. environment)
    • very dense mechanical boundary conditions
simple feb for the n xyter starter kit
"Simple" FEB for the n-XYTER Starter Kit
  • A simple hybrid PCB with signal fan-in, ADC and interconnect to SysCore DAQ chain
  • Allow development of the DAQ chain
  • Allow the readout of various detector prototypes

Allow to explore the challenges of hybrid development

The September beam time has shown the whole signal chain operative!

Silicon Strip / GEM Gas Detectors --- n-XYTER --- SysCore DAQ System

n xyter feb at the limits of pcb technology
n-XYTER FEB: At the limits of PCB-technology

Interference point of many technologies,

each imposing limiting boundary conditions:

  • Chip-In-Board solution avoids space eating vias
  • allows pitch adaptation:
    • 50,7 µm on chip to
    • PCB side 101,4 µm on two levels
n xyter feb at the limits of pcb technology5
n-XYTER FEB: At the limits of PCB-technology
  • 100 µm pitch on PCB is at the limit of PCB technology!
    • landing area for bonds comes out much smaller than 50 µm
  • high yield wire bonding technology finds limits at ~65 µm landing space
  • Chip-In-Board technologically impeeds use of cooling vias
    • Unplugged vias spoil bonding structures
    • Plugged vias spoil bonding surface quality
    • Current Solution: Macroscopic metal inlay underneath the chip realized after PCB manufacturing will give thermal link to cooling infrastructure



 Realize 125 µm pitch on PCB at the expense of more complicated fan-out bonding with Chip-In-Board, two layer bonding and metal in-lay cooling contact

 FEB-Rev D

it is all a question of yield
It is all a question of yield!
  • Wire Bonding Technology:
  • Maximum bond length ~ 4 mm
  • Staggered fan-out complicates bonding
  • Bonding machine determines specs on dimensions of landing space
  • PCB-Technology
  • 50µ / 50µ shatteres yield
  • close contact to manufacturer
  • special solutions (Chip in Board)
  • metal inlay solution
  • Home made issues:
  • -- Cooling strategy:
  • Wire bonds demand cooling from below
  • Flip-Chip bump bonds may allow cooling from either side
  • -- Limitations on Orcad layout tool
  • -- On Chip bond-pad layout
n xyter feb prototype gem tpc for panda
n-XYTER FEB Prototype - GEM-TPC for PANDA

Application foreign to CBM, but high density gas detector read-out, just like CBM-MUCH

  • Board status: in production

First large scale application of n-XYTER: 92 chips on 46 boards. Beam time for the TPC at FoPi: End of 2009

  • Dimensions: 265 x 103 mm
  • 8 layers

Slide by Rafal Lalik

n xyter quattro
n-XYTER Quattro

Integrated double sided Silicon Baby Sensor Readout

  • 4 n-XYTERs on one PCB
  • 100 x 100 mm2
  • 8 layers
  • SysCore read-out
  • complicated mechanical

milling scheme

Status:In production

at ILFA !

Slide by Rafal Lalik

sts specific hybrid developments
STS specific hybrid developments
  • Hybrid for STS Ladder Modules
  • Combined challenges with
    • high density chip assembly needs
    • sensitive microcable detector interconnect
    • integrated cooling
    • integrated powering scheeme in high magnetic fields and rad. env.
  • Temptatively, a completly different technology comes into play:
    • Silicon based circuit board
    • flip chip assembly of XYTERs
      • high efficiency cooling contacts and hybrid stackability
    • tap bonding for micro-cables (V. Pugatch, Kiev)
    • separated potential domain for upper and lower side det. readout
two development lines to be discussed
Two development lines to be discussed:
  • STS module based on n-XYTER and PCB technology
    • primarily to show micro cable performance
    • 4 to 8 chip hybrid, preferably dual side readout
  • STS module based on n-XYTER and compact flip-chip technology,
    • Silicon circuit board serves as
      • efficient cooling contact (cooling from both sides)
      • pitch adapter to the micro cables
  • Precise project definition and distribution of workpackages still to be done,
  • GSI Detectorlab signed up for hybrid development (we will have a new electronics engineer starting in December)
  • so we should now start this discussion