7-Segment Display: Spartan-3 board

1. 7-Segment Display:Spartan-3 board Discussion D3.3 Example 13

2. Spartan 3 Board

3. Spartan 3 Board

4. Turning on an LEDNote: A zero turns on the LED

5. Spartan 3 Board

6. 7-Segment Decoder a-g LOW to turn on segment

7. Multiplex displays

8. Multiplex displays 1 1 1 0 0 0 0 0 1 1 0

9. Multiplex displays 1 1 0 1 0 0 0 1 1 1 1

10. Multiplex displays 1 0 1 1 1 0 0 1 1 0 0

11. Multiplex displays 0 1 1 1 0 1 1 1 0 0 0

12. dig7seg and x7seg

13. library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; entity ancode is port ( aen: in STD_LOGIC_VECTOR (3 downto 0); asel: in STD_LOGIC_VECTOR (1 downto 0); an: out STD_LOGIC_VECTOR (3 downto 0) ); end ancode;

14. architecture ancode of ancode is begin process(asel) begin if(aen(conv_integer(asel)) = '1') then an <= (others => '1'); an(conv_integer(asel)) <= '0'; else an <= "1111"; end if; end process; end ancode;

15. dig7seg.vhd dig3 dig2 dig1 dig0 clk library IEEE; use IEEE.std_logic_1164.all; entity dig7seg is port ( dig0: in STD_LOGIC_VECTOR (3 downto 0); dig1: in STD_LOGIC_VECTOR (3 downto 0); dig2: in STD_LOGIC_VECTOR (3 downto 0); dig3: in STD_LOGIC_VECTOR (3 downto 0); clr: in STD_LOGIC; clk: in STD_LOGIC; aen: in STD_LOGIC_VECTOR (3 downto 0); a_to_g: out STD_LOGIC_VECTOR (6 downto 0); an: out STD_LOGIC_VECTOR (3 downto 0) ); end dig7seg;

16. architecture dig7seg of dig7seg is component mux44 port( a : in std_logic_vector(3 downto 0); b : in std_logic_vector(3 downto 0); c : in std_logic_vector(3 downto 0); d : in std_logic_vector(3 downto 0); s : in std_logic_vector(1 downto 0); y : out std_logic_vector(3 downto 0)); end component; component hex7seg port( x : in std_logic_vector(3 downto 0); a_to_g : out std_logic_vector(6 downto 0)); end component; component ctr2bit port( clr : in std_logic; clk : in std_logic; q : out std_logic_vector(1 downto 0)); end component;

17. component acode port( aen : in std_logic_vector(3 downto 0); asel : in std_logic_vector(1 downto 0); an : out std_logic_vector(3 downto 0)); end component; signal digit: STD_LOGIC_VECTOR (3 downto 0); signal count: STD_LOGIC_VECTOR (1 downto 0); begin

18. ---------------------------------------------------- -- Component Instantiation ---------------------------------------------------- u0: ctr2bit port map (clr => clr, clk => clk, q => count); u1: mux44 port map (a => dig0, b => dig1, c => dig2, d => dig3, s => count, y => digit); u2: hex7seg port map (x => digit, a_to_g => a_to_g); u3: acode port map (aen => aen, asel => count, an => an); end dig7seg; dig3 dig2 dig1 dig0 clk

19. Aldec Active-HDL Simulation

20. x7seg.vhd library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.std_logic_unsigned.all; entity x7seg is Port ( x : in std_logic_vector(15 downto 0); cclk, clr : in std_logic; a_to_g : out std_logic_vector(6 downto 0); an : out std_logic_vector(3 downto 0) ); end x7seg;

21. architecture arch_x7seg of x7seg is signal digit : std_logic_vector(3 downto 0); signal count : std_logic_vector(1 downto 0); signal aen: std_logic_vector(3 downto 0); begin aen <= "1111"; -- all digits on -- 2-bit counter ctr2bit: process(cclk,clr) begin if(clr = '1') then count <= "00"; elsif(cclk'event and cclk = '1') then count <= count + 1; end if; end process;

22. -- MUX4 with count select digit <= x(3 downto 0) when "00", x(7 downto 4) when "01", x(11 downto 8) when "10", x(15 downto 12) whenothers;

23. -- hex7seg with digit select a_to_g <= "1001111" when "0001", --1 "0010010" when "0010", --2 "0000110" when "0011", --3 "1001100" when "0100", --4 "0100100" when "0101", --5 "0100000" when "0110", --6 "0001111" when "0111", --7 "0000000" when "1000", --8 "0000100" when "1001", --9 "0001000" when "1010", --A "1100000" when "1011", --b "0110001" when "1100", --C "1000010" when "1101", --d "0110000" when "1110", --E "0111000" when "1111", --F "0000001" whenothers; --0

24. -- digit select acode: process(count) begin if(aen(conv_integer(count)) = '1') then an <= (others => '1'); an(conv_integer(count)) <= '0'; else an <= "1111"; end if; end process; end arch_x7seg;

25. Aldec Active-HDL Simulation