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Programmable Adaptive Router for GALS Parallel Systems in SpiNNaker Neural Simulation

This paper discusses the design and functionalities of a programmable adaptive router for a Globally Asynchronous Locally Synchronous (GALS) parallel system, specifically within the SpiNNaker architecture tailored for massive neural simulations. It outlines the requirements for fault tolerance, power efficiency, and bandwidth, highlighting features like adaptive routing for multicast, point-to-point, and nearest-neighbor packets. The architecture is designed for real-time operation with high throughput, supporting up to 1 billion neurons, and includes detailed discussions on packet checking, data flow control, and power distribution under varying loads.

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Programmable Adaptive Router for GALS Parallel Systems in SpiNNaker Neural Simulation

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  1. A Programmable Adaptive Router for a GALS Parallel System Jian Wu APT Group University of Manchester May 2009

  2. SpiNNaker System for Neural Simulation Node = SpiNNaker CMP + large off-chip memory • Massively-Parallel • (1 million ARMs) • Massive neural net simulations • (1 billion neurons in real time) • GALS infrastructure • Fault-tolerant

  3. SpiNNaker Chip

  4. Router Requirements • Operation requirements: • Route multicast, point-to-point and nearest-neighbour packets. • Reprogrammable at run-time. • Provide an external interface to system resources. • Fault-tolerant operation. • Power efficiency. • Bandwidth Requirements: ~7.4Gb/s • On-Chip traffic: (20-1)procs x 1000neurons x 72bit x 1000Hz = 1.368Gb/s • Inter-chip traffic: 1Gb/s x 6 links = 6Gb/s • Bandwidth Target = 72bit x 200MHz = 14.4Gb/s

  5. Router architecture • Packet checking: • - Check packet for errors and • enable appropriate routing engine • Multicast (MC) router: • - Route neural spikes according to their • source address • Point-to-Point (P2P) router: • - Route system management and control • information packets. • Nearest-neighbor (NN) router: • - Route system boot-up and debugging info • - Provide external I/F to resources • Adaptive routing: • - Redirect blocked packets • Router Interface to system NoC: • - AHB Master and Slave Interfaces

  6. Multicast Router

  7. Default and Adaptive Routing • Route packets “across chip” by default (save RT entries!) • Automatically re-route packets destined to congested or failed links

  8. Interfacing with System NoC • Nearest-Neighbour packets are diverted to the System NoC. • Programming data is sourced from the System NoC.

  9. Elastic Buffering • The spiking rate for the great majority of neurons is low -just a few Hz: Pipeline “bubbles” between valid packets. • There can be more than one request to the datapath issued in the same clock cycle. • The adaptive routing mechanism stalls the pipeline to find an alternative path for the congested packet. Simple, synthezisable design: • Use ordinary flip-flops for data latching. • Use a global, combinatorial circuit to generate stall signals

  10. Elastic Buffering Pipeline1 Pipeline2 Pipeline3 Disable Disable Disable Flag1 Flag2 Flag3 Back Pressure Pipeline Control Pipeline Control Pipeline Control

  11. Input Interchangeable Buffer • Used for flow control at the head of the pipeline. • One register is used in normal operation • The second is used when a stall occurs in the next stage • The delay is re-introduced when the stall is removed

  12. Parallel-Path Synchronizer Avoid 2-cycle penalty to increase throuhgput

  13. Packet Drop Rate

  14. Power vs. Traffic Load

  15. Power Distribution Power distribution under full traffic load Power distribution under 10% traffic load

  16. Thank you

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