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הפקולטה למדעי ההנדסה Faculty of Engineering Sciences. המחלקה להנדסת חשמל ומחשבים. Subthreshold SRAMs in 40nm techonology p-2010-062. Lidor Pergament & Omer Cohen Mr. Adam Teman , Dr . Alexander Fish. Lecture Contents. Introduction SRAM Overview Novel SRAM bitcell

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subthreshold srams in 40nm techonology p 2010 062

הפקולטה למדעי ההנדסה

Faculty of Engineering Sciences

המחלקה להנדסת חשמל ומחשבים

SubthresholdSRAMs in 40nm techonologyp-2010-062

Lidor Pergament & Omer Cohen

Mr. Adam Teman, Dr. Alexander Fish

lecture contents
Lecture Contents
  • Introduction
  • SRAM Overview
  • Novel SRAM bitcell
  • Test Chip Architecture
  • Summary
memory classification
Memory Classification

Memory is classified by 4 major categories

Volatility, Access Speed, Capacity and Cost

Volatile

Non Volatile

SRAM

DRAM

REGISTER

CACHE

FLASH

EEPROM

HARD DISK

motivation goal
Motivation & Goal
  • Minimum energy point in digital circuits is achieved at subthreshold voltages (Vdd < Vt).
  • Low-voltage operation of SRAM memories in the subthreshold region offers substantial power and energy savings at the cost of speed.
  • This project focuses on the design and implementation of a novel SRAM bitcell for use in the subthreshold region.
bistability butterfly curve
Bistability – Butterfly Curve
  • Positive feedback creates two stable points “1” and “0”.
  • Regenerative property ensures a noisy cell converges back to nominal values.
sram read access
SRAM – Read Access
  • Bitlines (BL, BL’) are precharged to VDD
  • Wordline signal (WL) is asserted
  • One of the bitlines is pulled down toward GND.
  • Differential signal (BL-BL’) is amplified to accelerate the process.

M1 > M5 Constraint!

sram write access
SRAM – Write Access
  • Bitlines are precharged to complementary values.
  • Worldline signal (WL) is asserted.
  • Q is pulled down to GND while Q’ is driven to VDD.

M6 > M4 Constraint!

sram subthreshold challenges
SRAM – Subthreshold Challenges
  • In general, ratioed digital circuits are more likely to fail in subthreshold voltages.
  • 6T Bitcells cannot operate below 600mV – 700mV.
  • Read SNM problem - degraded read noise margins decrease bitcell stability.
  • Write fails under 600mV due to the increase of the pMOS drive in sub-threshold.
the research work
The Research Work
  • Numerous novel low-power SRAM memories have been proposed in recent years.
  • We studied and analyzed many of the important proposals which include : 6T, 7T, 8T, 9T, 10T bitcells, Virtual VDD, Virtual GND, DCVSL, Voltage Boost, Read Buffer, Read Assist, Voltage Boost, and more …….
major achievements
Major Achievements
  • Two innovative SRAM 9T bitcells, named PSRAM and SFSRAM , aimed at eliminating static power consumption and operated in the subthreshold region were fully designed and analyzed.
  • Three types of 8-kb 40 nm SRAM test chips, nicknamed RAMBO, were designed for operation at 600mV and below.
  • We are the first academic research team inIsrael to fully design and fabricate a state-of-the-art 40nm CMOS silicon chip.
standard 8t schematic and layout
Standard 8T – Schematic and Layout

Schematic of a standard 8T SRAM bitcell

Stick Diagram of a standard 8T SRAM bitcell

pseudo sram psram
Pseudo SRAM (PSRAM)
  • Pseudo static behavior - A novel bitcell mechanism disposes of both data node charges while holding a logical “1”.
  • Leakage current is practically eliminated during this low-power standby mode.
  • Up to 3.75Xless static power consumption than a standard 8T cell at 0.9V.
psram write 1 operation
PSRAM – Write “1” Operation

WBL is driven to “1” and WBLB to “0”

CLK synchronizes write access

Write wordline (enable) is asserted

Q is driven to “1” and QB to “0”

Q is discharged to during standby

sfsram supply feedback sram
SFSRAM (Supply Feedback SRAM)
  • Enables subthreshold write with a Virtual-VDD technique – weakening the Supply VDD during write operation.
  • A new approach for the design of the Virtual-VDD scheme reduces periphery and thus, reduces write power.
  • Operates at ultra-low voltages, down to 200mV.
standard 8t revisited
Standard 8T – Revisited

Schematic of a standard 8T SRAM bitcell

Stick Diagram of a standard 8T SRAM bitcell

chip architecture
Chip Architecture
  • 8-kb Array
  • Read-Bitline division
  • Level Shifters
  • Row Decoder
  • Sense-Amps
  • Precharge Units
  • Write Drivers
  • BIST
40nm test chip periphery
40nm Test Chip - Periphery

Schematic of Sensing Unit + Up Shifter

Schematic of Write Driver

Schematic of WL Driver + Down Shifter

test chip top level layout
Test Chip Top Level Layout

2.90 um

1.40 um

1.40 mm

1.40 mm

chip timing diagrams
Chip Timing Diagrams

SRAM access is synchronized by a clock. Bitline Precharge, write driving and digital logic execute during the high phase and read/write take place during the low phase.

summary
Summary
  • A fully functional 8-kb array was layed out and designed for the 40nm lp TSMC process.
  • SFSRAM Memory successfully operates at subthreshold voltages - no additional periphery required.
  • Additional power savings can be achieved in the PSRAM with a majority bit algorithm.
summary continued
Summary – Continued
  • PSRAM consumes up to 3.75X less static power than a standard 8T cell.
  • We Are The first academic research team in Israel to fully design and fabricate a state-of-the-art 40nm chip.
questions
Questions??

Chocolate Chip

Digital Chip