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Memory Interface Analysis Using the Real-Time Model Checker UPPAAL

Aalborg University Computer science departement Software systems Engineering. Memory Interface Analysis Using the Real-Time Model Checker UPPAAL. Egle Sasnauskaite Marius Mikucionis Supervisor: Gerd Behrmann Co-cupervisor: Thomas Hune. 31 May, 2002. 2. 2`. 1. 1. 2´´. 1`. 1´´.

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Memory Interface Analysis Using the Real-Time Model Checker UPPAAL

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  1. Aalborg University Computer science departement Software systems Engineering Memory Interface Analysis Using the Real-Time Model Checker UPPAAL Egle Sasnauskaite Marius Mikucionis Supervisor: Gerd Behrmann Co-cupervisor: Thomas Hune 31 May, 2002

  2. 2 2` 1 1 2´´ 1` 1´´ e0,4 e1,4 2 e2,4 e0,3 e1,3 e2,3 e3,4 e0,2 e1,2 e3,3 e2,2 e3,2 e4,4 e3,4 e4,2 Motivation Radar principles: • Frequency diversity • Sweep integration MI system: (adders, FIFO buffers,register, an arbiter, SDRAM): • Synchronize. Storing data in the memory module • Combine Sliding window sum calculation Sum d,i=e d,i +sum d-1,i - e d-m,i

  3. The Main Goals • To analyse and to model the MI between input, output and the memory. • To verify the model within a reasonable amount of time and memory space. • To optimise the model in terms of buffer sizes and an arbiter algorithm. • To summarise the modelling methods for similar systems.

  4. Modelling • Modelling tool – UPPAAL (a modelling toolbox of symbolic simulation and verification) • The model of the MI is a combination of timed automata with UPPAAL extensions

  5. Verification • Model based techniques – Simulation and automated model checking • Verification method – Partial order reduction • Optimisation technique for full verification – Heuristical periodical approximation

  6. Partial-order Reduction Method • Purpose – to avoid combinatorial explosion of states due to the modelling concurrency by interleaving. • Implementation – by introducing additional components. • Gain: Event serialization order and determinism • Problem: State space is still too big to verify the model • Disadvantage: Only particular ordering is examined

  7. Heuristic Periodic Approximation • Purpose – to predict how many states should be explored to fully verify the model • Implementation: • find smaller subsystems in the compound system, • define periods of subsystems in a bigger system, • calculate the system period, which is expected to be the least common multiple of the subsystemperiods.

  8. A state of an automaton changes if changes: • Valuation of clocks • Valuation of data variables • Location of the automaton. S=(l, v) ai – delay-transition ai´ – action-transition Si ai Si+1 A Path A compressed path a0 a1 a`0 a1` ai … ai´ li,vi l0,v0 l0,v0´ l1,v1 l1,v1´ li,vi´ A state cycle lk+n-1,v´k+n-1 lk+1,vk+1´ lk+n-1,vk+n-1 l0,v0 ak+1 l0,v0´ lk+1,vk+1 lk,vk´ lk,vk a`k+1 ak` ak+n-1 ak a`0 … a0 … a`k+n-1 A period of a state cycle: Definitions in Heuristical Periodical Approximation

  9. Memory Interface Architecture Timer 2x100MHz Starter Bus1 10-100MHz Bus2 100MHz Arbiter 2x100MHz Buff0 Reg0 Buff1 Reg1 Buff2 Reg2 Adder1 Buff3 Reg3 Memory Buff4 Reg4 Buff5 Reg5 Adder2 Buff6 Reg6 Buff7 Reg7 Buff8 Reg8

  10. Serialization Example starter:=Starter(); timer:=Timer(21, 5, 3); bus1:=Bus(1, 0, wireCount0, 1, bus0Wire, begSig, endSig); buf0:=inBuffer(2, 0, 1024, 0, 0, 0, 1, bus0Wire, bus1Wire, begSig, endSig, 8, begBuff, endBuff, 32); buf1:=inBuffer(3, 1, 1024, 0, 1, 1, 3, bus0Wire, bus1Wire, begSig, endSig, 8, begBuff, endBuff, 32); buf2:=outBuffer(4, 2, 512, 512, 2, 5, 2, bus1Wire, bus0Wire, begBuff, endBuff, 32, begSig, endSig, 8); ... buf8:=inBuffer(10, 8, 2048, 0, 8, 8, 17, bus0Wire, bus1Wire, begSig, endSig, 16, begBuff, endBuff, 32); bus2:=Bus(11, 1, wireCount1, 1, bus1Wire, begBuff, endBuff); reg0:=Register(12, 0, 0, 0, 0, bus1Wire, begBuff, endBuff, begMem, endMem); reg1:=Register(13, 1, 2, 1, 0, bus1Wire, begBuff, endBuff, begMem, endMem); ... reg8:=Register(20, 8, 16, 8, 0, bus1Wire, begBuff, endBuff, begMem, endMem); arbiter:=Arbiter(0, 2, begMem, endMem);

  11. Periods in the Model Arbiter int counter; const unsafe 15625/5; const refreshCycle 100/5; const maxSafe unsafe-6; const maxUnsafe unsafe+refreshCycle;

  12. Period length: 640ns=27·5ns Cycle start: 80ns Cycle end: 720ns Buff0 Reg0 Memory Buff1 Reg1 Period length: 5760ns=27 ·32 ·5ns Cycle start: 520ns Cycle end: 6280ns Buff0 Reg0 Buff1 Reg1 Buff2 Reg2 Adder1 Buff3 Reg3 Memory Buff4 Reg4 Buff5 Reg5 Adder2 Buff6 Reg6 Buff7 Reg7 Buff8 Reg8 Small vs. Complete MI (without refresh)

  13. Small MI with Memory Refresh Verification space is proportional to LCM(PMI, PR)

  14. Complete MI with Memory Refresh 4E+6 The verification space can hardly be characterized by LCM(PMI, PR)

  15. Optimal Heuristic (fullest buffer) Non-deterministic Round-robin Arbiter Algorithm Synthesis (future) No halting problem for particular buffer sizes: If algorithm exists  it contains a finite cycle, since the number of states is finite If algorithm does not exist  buffer over/under-flow in all verification branches

  16. Conclusions • The biggest challenge - state explosion problem. • Proposed a UPPAAL model of MI which is small enough to verify with an approximate memory refresh timing. • The model is flexible for various configurations. • We used eight times smaller buffer sizes. • We introduced ideas for optimisations in the future.

  17. Questions?

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