JB Kuang and Keith Jenkins IBM Research June 2013

1. Mini-SRAM Test Structures:Distributed SRAM Yield Micro Probes for Monitoring 3D Integrated Chips JB Kuang and Keith JenkinsIBM Research June 2013

2. Author Details • JB Kuang is research staff member of IBM’s Austin Research Laboratory. His technical activities are in the area of high speed SRAM and eDRAM cache designs, double precision floating point logic, on-chip power supply generation, and most recently NAND Flash disk and memory appliances. • Keith Jenkins is research staff member of IBM’s Watson Research Center. His current activities include investigating the use of graphene for high-frequency integrated circuits, and developing on-chip circuits for in situ measurement of timing jitter, power supply transients, device variability and circuit reliability.

3. Extended Abstract 3D integration (3DI) offers increased interconnect bandwidth and cache/memory density, which can be in the form of high capacity DRAM, high performance SRAM arrays, or a combination of such. One challenge is the area efficiency trade-off, which is dictated by the native TSV pitch and keep-out distance between the TSV regions and active silicon area. It is desirable to observe SRAM cells in real time, across chip dimensional span or even on a stratum, due to SRAM’s extreme sensitivity to even parameter variations and device sizes. This work describes a small physical footprint, distributed on-chip observation infrastructure, which monitors SRAM in the vicinity of TSV regions. Information on locality specific Vt variation, read current fluctuation, and power supply sensitivity can be easily extracted either for fabrication facility tuning or customized on-chip operating configuration settings. Our implementation choice is in the matured 45nm SOI technology with high SRAM cell yield and stable baseline planar technology characteristics. In this fashion, we isolate contributions from the baseline 2D technology and observe issues directly attributed to the unique features of 3DI. The short ring ensures one unique undisputed frequency and correlation with the TSV neighbor. In summary, the proposed on-chip monitoring methodology demonstrates (1) the effectiveness of short-loop compact sized SRAM oscillators to achieve yield and DFM enhancements; (2) the availability of density margins for 3DI physical design rule optimization; (3) opportunities of intra- and inter-stratum location dependent parametric optimization in a large 3DI system.

4. Motivation • There is a need to understand the interaction between through-silicon via (TSV) stress and SRAM device/cell behavior in 3D integration. • TSVs may induce VT shift or aggravate VT scatter from random dopant fluctuation and process variations. • DFM-oriented test structures can reflect actual device usage and circuit style to flag potential yield detractors. • It is highly desirable to maximize usable silicon area in each stratum, guide the design rule optimization, and is environmentally green and fiscally responsible to minimize 3D hardware iterations. 4

5. The Approach • Create a small SRAM-like test circuit which: • Uses unaltered SRAM cells. • Uses real local evaluation circuit. • Captures word line to cell evaluation read timing. • Operates with the correct supply voltages (VDD, VCS). • Allows standalone operation with a minimal number of input signals, which can be controlled by scan latches. • Is small enough that it be easily placed in strategic locations on every stratum of interest. • Simplicity: use only 5 inputs and 1 ring output per instance 5

6. Placement of Test Structures • Basic idea: explore impact of distance to TSV SRAM device performance. • Ring Oscillator made up of the internal SRAM timing path! Active Silicon real estate 6

7. The Building Block 7

8. Small Profile Monitor Test Structure Active Read Access Path • 4 active SRAM cells make one observation point • Measured array electrical effect < half TSV width • Even columns, active; odd columns, wiring only

9. Array in Test Structure • 4x32 (6x34 actual) petite sub-array with built-in control infrastructure. blc (active cell 0 side) wla group Legend lvl-shift wl drv active wl accessed cell wlb group active local eval global eval-like enable global bl output 9

10. Placement of Mini-probe Instances Cases of most Intrusion into keep-out region Cases of half-way Intrusion into keep-out region Cases of least Intrusion into keep-out region

11. Reference Shmoo Diagram pass For a 14MB Functional SRAM on the same wafer with identical peripheral circuitry and subarray construct style VCS(V) fail VDD(V) 11

12. Simulated Waveforms for Evaluating Bit Lines Oscillator frequency dictated by bit line evaluation 12

13. Measurement Results An example of ring-by-ring SRAM-RO frequencies Measured on chips with TSVs Average frequency comparison for chips with and without TSVs

14. Measurement Results –Relative Frequency difference between TSV and non-TSV wafers before and after the annealing process*omission of annealing causes increase of PFET Vt Before annealing After annealing

15. Conclusion Distributed self-oscillating mini-probes are proven effective in detecting chip level as well as locale dependent parameter variations. The average SRAM ring oscillator frequency for all rings of TSV-chips is lower, by a small percentage, on a wafer with known stress induced pFETVt shift. Such wafers also show strong dependence (a few percent) on the proximity of the TSV to the active cells. These mini-probes aid yield parametric characterization on 3DI chips.