JAZiO ™ Incorporated JAZiO

1. Digital Signal Switching Technology JAZiO™ Incorporated www.JAZiO.com

2. Agenda: • What is JAZiO? • What’s Wrong with Traditional Methods of Signal Switching? • The JAZiO Solution

3. What is JAZiO? • JAZiO, Inc is a small San Jose-based company that invents and licenses technology • The first technology offered is Digital Signal Switching • This technology works with any user defined protocol, allowing complete product differentiation

4. Next bit time One bit time tRF tSU tHD Sharp Edges Cause: All information is transmitted during tRF (1/3 of bit time) Ground Bounce! Cross Talk! Ringing! EMI! High Power! The rest of the bit time is just wasted! Traditional Signal Driving

5. Traditional Signal Sensing Single ended: Not suitable for high speed Differential: Great!, but 2x the pins Pseudo differential: A compromise

6. Next bit time One bit time VREF Switching Level  0.8V Sensing Level Large switching levels cause: Sensing level about 1/3 of switching level Ground Bounce! Cross Talk! Ringing! High Power! The rest of the switching level is just wasted! Pseudo Differential Signal Sensing

7. Traditional Signal Switching Results in large, fast edges (high slew rate) Why is this important???? From Signal Integrity Corner, Be Afraid, Be Very Afraid By Eric Bogatin, www.bogatinenterprises.com • There are two kinds of designers, those that have signal integrity problems, and those that will • It is predominantly the rise time that influences the magnitude of signal integrity problems in a system.

8. Why Does this Matter? • Moore’s law: Silicon technology doubles every 18 months • Moron’s law: Non-silicon technology doubles every 18 years • Therefore transmitting data between chips (across motherboard, over cables, down backplane, etc) becomes the performance bottleneck of the entire system

9. What is Needed? • A system with edges that take most of the bit time • A system with small signal levels similar to true differential sensing • A system with 1 pin per signal How???

10. JAZiO Solution • JAZiO has invented a system which • Achieves very high performance • Has edges which can take the whole bit time • Uses differential sensing with very low signal levels • Yet has only 1 pin per data signal

11. What’s the Secret? A Re-think • For each data signal, there is either a change or no-change from the previous bit time • Traditional systems are good on no-change but bad on change • JAZiO looks for change first and then adjusts if no-change occurs • For JAZiO the decision binary is change or no-change rather than “high” or “low” relative to VREF

12. Provide alternating Voltage/Timing References switching at the data rate VTR VTR 3 7 Data is driven coincidentally with Voltage/Timing References Data Input 1 5 2 6 8 4 8 different combinations of VTR and Data Input One Bit Time Next Bit Time A Dual Comparators are used VTR Data Output Steering Logic B Data Input VTR JAZiO Solution In cases 1 and 6 Comparator A makes a differential comparison In cases 2 and 5 Comparator B makes a differential comparison In the other four cases Data Input does not change

13. Steering Logic The trick is to know how to select between Comparators A and B and what to do when Data Input does not change

14. A out in VTR XOR in Data Output Data Input B in out in VTR XOR VTR SL VTR SL VTR Steering Logic • Generate Steering Logic signals (SL and SL) • Use them with Data Output from previous Bit Time to select between Comparators A and B

15. Data Input Data Input VTR XOR SL Initialization or Receiver Enable Data Output SL XOR VTR 55 Transistors Per Bit

16. A out in VTR XOR in Data Output Data Input B in out in VTR XOR VTR SL Determine no-change and switch to Comparator B VTR SL VTR First Look for change Data Input  0.5V VTR Time Domain Decision is made in the Time Domain rather voltage domain

17. out in XOR-A in Data Output B VTR in out in XOR-B Data Input VTR SL VTR Both Comparators have Signal in No-change Case VTR SL VTR Initialize 0 1 1 0 0 1 Data Input VTR VTR Rail to Rail CompA SL CompB SL XOR-A Comparator Selected Rail to Rail Change? XOR-B B A A Yes No Yes No Yes Yes Data Output Rail to Rail JAZiO™ Receiver Operation A

18. A VTR out in SL XOR-A Data Output in Data Input (High) B in VTR out in SL XOR-B Bit Time 3 But! The handoff from Comparator A to B is smooth since both of them want to drive Data Output high After the handoff, Comparator B is ready to make the next differential comparison Since Comparator A is selected its high value causes Data Output to remain high The No-Change Case Comparator A is selected and as the differential on its inputs disappears the output remains high temporarily However, Comparator B is gaining a differential and its Output becomes a solid high But eventually the XORs will switch And Comparator B will be selected

19. Data Output 17 Data Output 9 Data Output 8 Data Output 0 XOR XOR SL SL XOR XOR XOR XOR XOR XOR Bits 10-16 Bits 1-7 SIGNALS FROM PADS VTR VTR Data Input 0 Data Input 8 Data Input 17 Data Input 9 18 JAZiO™Receivers

20. One bit time 1/3 bit time Traditional Approach  0.8V Same Slew Rate JAZiO  0.5V ~5 bit times Performance JAZiO is ~5 times faster

21. Power • JAZiO has lower switching levels and lower termination voltage • Instead of 1.8 to 1.0V use 1.0 to 0.5V  ~1/3 the Power • Slow edges  Lower current, smaller drivers • Only one pin per signal is used • One transition per data bit • No encoding JAZiO is ~1/3 the power

22. Robustness • JAZiO works best with slow edges (use the entire Bit Time!) • JAZiO works with small transition levels (differential sensing) • JAZiO is entirely common-mode • Works with any appropriate Termination Scheme (Series, Parallel, Single, Dual, Source and even none in some applications) JAZiO is very robust and easy to use

23. 10G • Slower edges • Lower switching levels • Reduced slew rate JAZiO™ Better JAZiO™ 1G JAZiO™ RDRAM Data Rate per Pin (b/S) DDR SDRAM-100 100M SDRAM-66 EDO-33 10M 0.5 1.0 1.5 2.0 2.5 3.0 3.5 Slew Rate (V/nS) Data Rate vs Slew Rate Comparison Higher Performance at Lower Power with Higher Robustness

24. Where Can JAZiO Be Used? • DRAM • SRAM • Front Side Bus • Backplane • Communications • On-chip Bus • Etc

25. How Can JAZiO Be Used? • JAZiO is “essentially” an Open Standard • All technology is publicly visible • Anyone can see it, study it, simulate it, design it in, build test chips, build prototypes, etc • Just don’t sell products without licensing it • JAZiO is working with JEDEC/AMI2 and is currently offering a license fee of $200K with royalty of 0.3% for DRAMs

26. Conclusion • JAZiO uses lower levels and slower edges • Achieves high performance, low power, high robustness • JAZiO technology is fundamentally different from traditional methods • Time domain rather than voltage domain • Look for change first • Change vs No-change rather than High or Low • JAZiO is available to everyone at low cost and applies to any application