Timers - 2

1. Timers - 2

2. Output Unit • Each capture/compare block contains an output unit. The output unit is used to generate output signalssuch as PWM signals. Each output unit has eight operating modes that generate signals based on theEQU0 and EQUx signals. • Output Modes

3. Timer in Up Mode • The OUTx signal is changed when the timer counts up to the TACCRx value, and rolls from TACCR0 tozero, depending on the output mode.

4. Timer in Continuous Mode • Timer in Continuous Mode

5. Output Unit • The TACCTLn registers are cleared by a power-on reset (they are not affected by apower-up clear). • Interrupts from Timer_A • Interrupts can be generated by the timer block itself (flag TAIFG) and eachcapture/compare channel (flag TACCRn CCIFG or CCIFGn for short). TACCR0is privileged and has its own interrupt vector, TIMERA0_VECTOR. Its priority ishigher than the other vector, TIMERA1_VECTOR, which is shared by the remainingcapture/compare channels and the timer block.

6. Measurement in the Capture Mode • The Capture mode is used to take a time stamp of an event;to note the time at which itoccurred. A measurement typically requires two or more captures. The timer can be used in two opposite ways, • In most cases the timer clock is either ACLK or SMCLK, whose frequency isknown, and the unknown signal is applied to the capture input. To measure thelength of a single pulse, we should capture both edges and subtract the capturedtimes. This gives the duration of the pulse in units of the timer clock’s period. Fora periodic signal we might capture only the rising edges (or falling if preferred)and the difference gives the period directly. The period of the timer clock shouldbe much less than the duration of the signal to give good resolution. • The opposite approach is used to measure a signal with a high frequency. Thesignal is used as the timer clock and the captured events are typically edges ofACLK, whose frequency is known. The difference between that and the capturedvalue gives the number of cycles of the signal in one cycle of ACLK. This givesthe frequency rather than the period. • The first method is much more common.

7. Measurement of Frequency: Comparison of SMCLK and ACLK • The general principle for measuring a frequency f is to count the number of cycles N in aknown interval of time T , whence f = N/T . If T = 1s then Ngives the frequency in hertz directly. Alternatively, if T = 1 ms then N gives the frequencyin kilohertz. • The signal under test is used as the timer clock and an external signal should be applied tothe TACLK pin. Remember to set the PnSEL.x bit to connect this pin to the timer andselect TACLK or INCLK using the TASSELx bits. • The channel is configured to capture the value of TAR and request an interrupt at a risingedge of ACLK. This value N1 is stored during the ISR. The next rising edge of ACLKstimulates another capture and interrupt. The difference between the new and old values ofTAR, N2−N1, gives the number of cycles of the test signal in one cycle of ACLK. Thusthe measured frequency is f = (N2−N1)fACLK.

8. Output in the Continuous Mode • In the Continuous mode, TAR counts from 0 up to 0xFFFF and returns to 0 on the nextclock transition, setting TAIFG as it does so. The only control over the period of TAR inreal time is through the choice of clock, which is so coarse that it will rarely give thedesired value. Therefore the duration of output signals must almost always be controlledby software rather than the period of the timer.

9. Pulse-Width Modulation • Microcontrollers are often required to vary the power supplied to a load through acontinuous range, not just on or off. This might seem to call for a digital-to-analogconverter, or DAC, but very few microcontrollers contain true DACs. A few MSP430sprovide them but most do not. The reason is that pulse-width modulation, or PWM,provides an adequate substitute for a DAC in most applications. It requires only a timer,which is purely digital and therefore much simpler and cheaper to fabricate than the analogcircuits required for a DAC. • The idea behind PWM is very simple: The load is switched on and off periodically so thatthe average voltage has the desired value. The fraction of the time while the load is activeis called the duty cycle D. Assume that the output isdriven either to ground or to VCC. Then the average voltage across the output is given by

10. PWM • Edge-aligned pulse-width modulation

11. Simple PWM • The usual arrangement for PWM is that each output is turned on when TAR returns to 0and turned off after a variable time that gives the desired duty cycle. This means thatincreasing the value in TACCRn increases the duty cycle, which makes the operationsimpler to understand. This needs the Reset/Set output mode (7)for loads driven active high. This is sometimes called positive PWM. Conversely, theSet/Reset mode (3) should be used for active low loads or negative PWM. • The duty cycle is given by

12. Design of PWM • There are two main parameters that must be chosen before suitable values can be selectedfor PWM: • The number of desired values of the duty cycle (the resolution). • The frequency of the output waveform. • These are linked because it is not possible to have both high resolution and a highfrequency. • Suppose that the duty cycle of the output is specified in percent to the nearest integer. Thismeans that there are 101 possible values of 0, 1, 2, . . . , 99, 100%. The simplest way ofhandling this is to choose TACCR0 = 99, which gives a period of 100 counts. The desiredduty cycle in percent can then be written directly to TACCRn for channel n (wheren > 0). Remember that the denominator for the duty cycle is(TACCR0+1).

13. Design of PWM • The appropriate frequency fPWM of the output waveform depends strongly on the type ofload. Anything higher than about 100 Hz is sufficient for an LED. The period of the PWMis the same as that of the timer and the frequency is therefore given by • This means that ftimer clock must be above 100 Hz×100 counts = 10KHz for the LED.There would be no problem in running the timer fromACLK at 32 KHz except that 10 KHzis not readily available. The simple options are fACLK/2 = 16KHz or fACLK/4 = 8 KHz.It would be better to choose the higher frequency to avoid visible flashing of the LED.