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Heavy Ion Irradiation of SRAM-based FPGA’s

Heavy Ion Irradiation of SRAM-based FPGA’s M. Ceschia 1 , M. Bellato 2 , J. Wyss 3 , M. Menichelli 4 , A. Papi 4 and A. Paccagnella 1,2 1 Dipartimento di Elettronica e Informatica, Università di Padova, via Gradenigo 6a, 35131 Padova, Italy

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Heavy Ion Irradiation of SRAM-based FPGA’s

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  1. Heavy Ion Irradiation of SRAM-based FPGA’s M. Ceschia1, M. Bellato2, J. Wyss3, M. Menichelli4, A. Papi4 and A. Paccagnella1,2 1 Dipartimento di Elettronica e Informatica, Università di Padova, via Gradenigo 6a, 35131 Padova, Italy 2 Istituto Nazionale di Fisica Nucleare, Sezione di Padova, via Marzolo 6, 35131 Padova, Italy 3 Dipartimento di Ingegneria, Università di Cassino, via G. DiBiasio 43, 03043 Cassino, FR, Italy 4 Istituto Nazionale di Fisica Nucleare, Sezione di Perugia, via A. Pascoli, 06100 Perugia, Italy

  2. Outline • Introduction • Experimental set-up • SEFI’s in FPGA’s • DC supply current during irradiation • Configuration memory Cross Section • Conclusions

  3. Introduction • Slow evolution of rad-hard devices • Rapid evolution of CMOS technology / COTS FPGA’s • Evolution of EDA tools and IP industry Use of commercial FPGA’s in radiation harsh environments Necessity to perform radiation tests on large FPGA’s (usually SRAM-based) and to develop software error detection and mitigation techniques

  4. Experimental /1 DEVICE UNDER TEST: • ALTERA FLEX FPGA: EPF10K100GC503-3 • 100,000 equivalent gates • 5,000 Logic Elements • 620 Logic Array Blocks • 25,000 Embedded Array Bits • 503 pin ceramic package • CMOS SRAM configuration memory

  5. Experimental /2 RADIATION SOURCES: • Heavy ions from Tandem van der Graaff accelerator: From 12C, E=88 MeV, LET= 1.6 MeVcm2/mg to 127I, E=257 MeV, LET= 62 MeVcm2/mg • Depending on the ion species the flux has been set between 20 ions/cm·s and 10,000 ions/cm·s MEASUREMENTS: • SEU / SEFI rate by monitoring signals from FPGA under test • SEL rate by monitoring supply current and turning off the power supply when Icc>800 mA

  6. 16 bit SHIFT reg. CLK 30 MHz Compare Error Latch Q1 16 bit SHIFT reg. TMR Signal gen. (Counter) TRIG Load Data Compare Q2 Error Latch 16 bit SHIFT reg. TMR Compare Q3 Error Latch 16 bit SHIFT reg. FPGA configuration under test Design has been fully implemented in the FPGA under test

  7. TRIG Q1 Q2 Q3 Output signals • SEFI’s happen long before any observable SEU in the flip-flops of the SR • We introduce the definition of First Error and Last Error: First Error (FE) Last Error (LE)

  8. 10-2 10-3 Device Cross Section (cm2) 10-4 10-5 0 5 10 15 20 Measurement # Device Cross Section of First Error 158 MeV Si ions, LET=8.5 MeV cm2/mg Measurements obtained by using low fluxes (~ 20 ions/cm·s). Data show statistical dispersion over two decades

  9. 0.9 0.8 0.7 0.6 0.5 0.4 0.3 Probability density (cm-2) 0.2 0.1 Experimental Data 0 10-6 10-5 10-4 10-3 10-2 10-1 Gaussian Distribution Device Cross Section (cm2) Probability Distribution 158 MeV Si ions, LET=8.5 MeV cm2/mg Gaussian distribution seems a reasonable model to describe the data dispersion

  10. 10-3 Device Cross Section (cm2) 10-4 10-5 0 5 10 15 20 Measurement # Device Cross Section of Last Error 158 MeV Si ions, LET=8.5 MeV cm2/mg LE Cross Section is about 10 times lower than FE Cross Section Statistical dispersion of data is similar to that measured for FE

  11. 10-9 10-10 Cross Section per bit (cm2) 10-11 10-12 0 5 10 15 20 Measurement # LE Cross Section per bit 158 MeV Si ions, LET=8.5 MeV cm2/mg We have evaluated the Cross Section per bit of configuration memory by supposing that all the configuration memory is corrupted when the LE is detected In an EPF10K100 there are about 1,200,000 configuration bits

  12. 10-2 10-3 10-4 Device Cross Section (cm2) 10-5 10-6 10-7 0 2 4 6 8 10 10-8 LET (MeV cm2/mg) Device Cross Section (FE and LE) The difference between FE and LE Cross Section is constant and about one order of magnitude First Error Last Error

  13. 10-1 10-2 10-3 10-4 Device Cross Section (cm2) Weibull fit 10-5 10-6 0 20 40 60 80 10-7 LET (MeV cm2/mg) 10-8 Device Cross Section (taken from SEL @ 800 mA) Weibull fit: F(L)=Fsat (1- exp{-[(L-L0)/W]s}) Fsat=3.1·10-2 cm2 L0=0.1 MeV · cm2/mg W=32 s=5

  14. 650 600 F E 550 D C 500 B A 450 Icc (mA) 9 Error Code 8 400 7 350 6 5 300 4 3 LE 250 Code TRIG Q1 Q2 Q3 2 1 200 E KO OK OK OK 0 0 200 200 400 400 600 600 800 800 1000 1000 1200 1200 1400 1400 9 OK OK KO KO Time (s) Time (s) 1 OK KO KO KO Supply Current / 1 109 MeV O ions, LET=2.8 MeV cm2/mg LE Supply current increases gradually during irradiation (no SEL, seemingly but likely due to degradation of the configuration memory)

  15. 800 700 Code TRIG Q1 Q2 Q3 LE 3 OK KO KO OK 3 600 1 OK KO KO KO Icc (mA) 500 Error Code 2 400 LE 1 300 200 0 0 200 200 400 400 600 600 800 800 1000 1000 Time (s) Time (s) Supply Current / 2 109 MeV O ions, LET=2.8 MeV cm2/mg Supply current sudden increases after 730 s => SEL?

  16. 10-1 10-8 10-2 10-9 10-3 10-10 10-4 Cross Section per bit (cm2) Device Cross Section (cm2) Weibull fit 10-11 10-5 First error 10-12 10-6 10-13 Last error 10-7 10-14 10-8 Power Supply switched off (Icc>800mA) 0 20 40 60 80 LET (MeV cm2/mg) Device Cross Section (from FE, LE and P.S. switch off) (LE)  (Icc>800mA) (FE) > (LE)

  17. Conclusions • First heavy ion testing of SRAM-based Altera FPGA’s • Circuits based on four Shift Registers have been designed to test the single event effects • Only SEFI errors have been detected; destructive SEL was avoided by using a protection circuit • These SEFI’s are due to SEU in the configuration memory • Supply current increase: both gradual and step-like (SEL’s?) have been observed • Cross Section per bit found for these Altera devices is similar to that found for Xilinx Virtex FPGA’s

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