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Polar-Demo Electronics

Polar-Demo Electronics. Aliko mtchedlishvili, Wojtek Hajdas, Estela Suarez, PIE…. General schematics FPGA structure Data flow Status. PM. PM. ASIC 1. ASIC 2. JTAG. RS232. Flash prom. Power pc. Virtex4 FX60. Exp DSP. SRAM 512 KW. SRAM 512 KW. Power control. voltage and current

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Polar-Demo Electronics

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  1. Polar-Demo Electronics Aliko mtchedlishvili, Wojtek Hajdas, Estela Suarez, PIE… General schematics FPGA structure Data flow Status

  2. PM PM ASIC 1 ASIC 2 JTAG RS232 Flash prom Power pc Virtex4 FX60 Exp DSP SRAM 512 KW SRAM 512 KW Power control voltage and current controll General schematics ADC DAC ADC DAC USB M/SLAVE

  3. VA64MaPMT Channel Architecture

  4. Effect of adjusting Vfs and Sha_bias Control register

  5. Overview of the ASIC Back End and Calibration circuitry.

  6. interface FPGA structure and data flow Coincidence ADC IF ADC IF ASIC control. I2C DAC IF I2C DAC IF digital Discr. Progr. control. Trigger status activ. SPI Power RS232 USB 2 SRAM IF

  7. Trigger generation • Permanent checking of time interval • Programmable Time interval • Programmable number of pixels • Programmable number of clusters • Wait for first events • Programmable Time interval • Programmable number of pixels • Programmable number of clusters

  8. Pixel processing algorithm • Accept events in coincidence interval (programmable) • Find number of active pixels • If min<N>max check position of pixels • Check number of clusters • Check Amplitude of signals, if for all clusters Amplitude > max – reset and wait for new event • If some clusters have Amplitude < max -- create telemetry packet, save or transmit to SC • Wait for next GRB?

  9. Status Schema of Design +Layout of Design -+Card production and assembling -Diagnostic software +Diagnostic firmware -+Final firmware and complex test -

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