Pelican IP Pictures

1. Pelican IP Pictures ComLSI Inc. Confidential and Proprietary information

2. DRX-Term.(Shared) Mode IO 3.3v 1.8v to 3.3v Core 1.8v Serial data in PDN Level Shift Pre- Drive DTXFE DVI Tx Confidential / Proprietary

3. Mode DRx-Term. 3.3v to 1.8v Core 1.8v Core 1.8v Serial data out PDN Level Shift Latch DRXFE DR-DLL PhaseDetect Dly Ctrl Delayed Sample CLK DR-Delay 10x CLK DVI Rx Confidential / Proprietary

4. DVI Rx Specifications Confidential / Proprietary

5. DVI PHY Confidential / Proprietary

6. AVCC VDD 10 ZR2 ZR1 ZT2 ZT1 LINK 15 9 14 13 8 VP 12 3 Driver 4 VN S3 S4 shield Interconnect and far-end termination 1 2 VP 11 S1 S2 5 VN LINK AVCC S1 S2 6 50 R2 R1 50 Interconnect and far-end termination Is Line driver 7 Is 0 3 R ZX XL 1 2 Gen - 2 Patent-pending SCDL driver Prior art Confidential / Proprietary

7. LRX-Term. (Shared) Mode Differential IO 1.8v Core 1.8v Serial data in PDN SE - Diff Conv. Pre- Drive LTXFE EQPre-Drv LTx-EQ LVDS Tx Confidential / Proprietary

8. LVDS Tx Specifications Confidential / Proprietary

9. Mode LRX-Term. PDN Data Capture Core 1.8v Serial data out Equalizer Digitizer Latch LRXFE LRXGain Bit Capture CLK DR-DLL PhaseDetect Dly Ctrl Delayed Sample CLK DR-Delay 10x CLK LVDS Rx Confidential / Proprietary

10. LVDS Rx Specifications Confidential / Proprietary

11. CBDS PHY Confidential / Proprietary

12. VDD R2 50 R1 50 50 R3 R4 LINK S1 S2 + + – – Is VDD 6 19 VPB 15 25 5 PUP PEU NUP NEU PAMP 7 IREF 8 17 23 21 11 VCOM 13 12 ON OP 14 22 2 18 24 NAMP 9 4 VREP PDN PED NDN NED VNB 16 26 10 1 3 20 0 Key innovation - CBDS Patent-pending CBDS architecture Prior art Confidential / Proprietary

13. Vplla 6 2 Vplld VDD VRA VRD 8 VPLLA Filter 12 7 Input Filter VPLLD Filter 4 10 5 3 9 PFD REF CP VCO LF FB VSS Divider 1 11 PLL (with VRA, VRD) Patent-pending architecture Confidential / Proprietary

14. PLL Specifications Confidential / Proprietary

15. HDMI Clock Synthesizer PLL Confidential / Proprietary

16. 2 1 0 2 1 0 HS Shift Reg HS Shift Reg HS Shift Reg HS Shift Reg HS Shift Reg HS Shift Reg Tx Tx Rx Rx Serializer / Deserializer - 2 Confidential / Proprietary

17. Serdes block Confidential / Proprietary

18. Data recovery DLL & loop Patent-pending DRDLL architecture Confidential / Proprietary

19. References • DVI_10.PDF: Digital Visual Interface Revision 1.0. 02 April 1999 • Hogge Jr., Charles R., “A Self Correcting Clock Recovery Circuit”, IEEE Journal of Lightwave Technology, vol. LT-3, pp. 1312-1314, December 1985 • Maneatis, John G., “Low-jitter process-independent DLL and PLL based on self-biased techniques”, ISSCC 199 Dig. Tech. Papers, Feb. 1996, pp. 130-131 • Balan, Vishnu et al, “A 4.8-6.4-Gb/s Serial Link for Backplane Applications Using Decision Feedback Equalization”, IEEE Journal of Solid-State Circuits, Vol. 40, No. 9, September 2005 • Sorna, M. et al, “A 6.4Gb/s CMOS SerDes Core with Feedforward and Decision-Feedback Equalization”, 2005 IEEE International Solid-State Circuits Conference • Razavi, B., “Monolithic phase-locked loops and clock recovery circuits Theory and Design”, IEEE Press 1996 • Gai, Weixin et al, “A 4-Channel 3.125Gb/s/ch CMOS Transceiver with 30dB Equalization”, 2004 Symp. On VLSI Circuits Digest of Tech. Papers, pp. 138-141 • Zerbe, Jared L. et al, “Equalization and Clock Recovery for a 2.5-10-Gb/s 2-PAM/4-PAM Backplane Trasceiver Cell”, IEEE Journal of Solid-State Circuits, Vol. 38, No. 12, Dec. 2003 • Rahman, H. and Islam, Syed K., “Fully-differential, high-speed current-mode controlled dividers designed using modular approach”, Internet document (publication unknown) • Lee, Chang-Hyeon et al, “Design of Low Jitter PLL for Clock Generator with Supply Noise Insensitive VCO”, IEEE, 1998 • Hannah, Eric C., “Method and apparatus to transmit signals over a cable”, US Patent 6,452,975 Sep. 17, 2002 • Bazes, et al, “Adaptive equalization using a minimum-jitter method”, US Patent 5,991,339 Nov. 23, 1999 • Henning Braunisch and Raj Nair, “On the Techniques of Clock Extraction and Oversampling” Confidential / Proprietary