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EKT 221 : Digital Elect 2. QUIZ. Modify the register of figure shown so that it will operate according to the following function table using mode selection inputs and. Datapath and Control. Control Unit - Determines the enabling and sequencing of the operations.
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QUIZ Modify the register of figure shown so that it will operate according to the following function table using mode selection inputs and .
Datapath and Control • Control Unit - Determines the enabling and sequencing of the operations • Datapath - performs data transfer and processing operations The control unit receives: – External control inputs – Status signals The control unit sends: – Control signals – Control outputs
Types of Control Unit • 2 types: • Programmable • Non-programmable • Programmable System • Input consist of sequence of instructions • Instruction are usually stored in memory (RAM or ROM) • Address comes from PC (Program Counter) • Non-programmable (This chapter FOCUS on this) • Control unit is NOT responsible for getting instructions from memory or sequencing hence NO PC • CU determine the operation based on inputs and status bit from the datapath.
ALGORITHMIC STATE MACHINE(ASM) • A Flowchart is a convenient way to specify a sequence of procedural steps and decision paths for an algorithm. • ASM chart provides not only sequence of events, but it distinguished by the fact that it describes the timing relationship between states of the CU and the datapath actions in response to clock pulses.
ASM Chart • 4 basic elements: • State box • Scalar decision box • Conditional output box • Vector decision box
ASM Chart : State Box • Consist of a rectangle with: • The symbolic name for the state marked outside the upper left top • Containing register transfer operations and outputs activated within or while leaving the state • An optional state code, if assigned, outside the upper right top Entry Exit
ASM Chart : State Box Explanation : • The register transfer indicates that the register R is to be reset to 0 on any clock pulse that occurs while the control is in state IDLE. • RUN indicates that the ouput signal RUN is to be 1 during the time that the control in in state IDLE. Entry Exit
ASM Chart : Scalar Decision Box (Refers to 1 bit condition) • Consist of a diamond with: • One input path (entry point). • One input condition, placed in the center of the box, that is tested. (in this case START) • A TRUE exit path taken if the condition is true (logic 1). • A FALSE exit path taken if the condition is false (logic 0). Entry Exit 0 Exit 1
ASM Chart : Conditional Output Box • Consist of an oval with: • One input path from a decision box or decision boxes. • One output path • Register transfers or outputs that occur only if the conditional path to the box is taken.
Entry Exit 2 Exit 0 Exit 2n - 1 Exit 1 ASM Chart : Vector decision box • Consist of a hexagon with: • One Input Path (entry point). • A vector of input conditions, placed in the center of the box, that is tested. • Up to 2n output paths. The path taken has a binary vector value that matches the vector input condition
ASM Block • Consist of ONE State box and all of the decision and conditional output box connected between the state box exit and entry paths to the same or other boxes. Figure 8.2 : Morris Mano, pg 367
ASM Block ANALYSIS: • State IDLE, AVAIL = 1 • START = 0, next state is IDLE • START = 1, next state, A is cleared to all 0’s • Depending on value of Q(1:0), next state is MUL0, MUL1, MUL2 or MUL3. • Note : The entry path and the five exit paths for the ASM block is labeled at the boundaries of the ASM block
ASM Block : Another Example ANALYSIS: • State IDLE, AVAIL = 1 • START = 0, next state is to Increase R and next state is IDLE • START = 1, next to clear R to all 0’s and next state is… • Depending on value of Q0, next state is MUL0 or MUL1.
ASM Timing Considerations • Refer to Figure 8.2 • Using PGT, the timing diagram below is obtained. Fig. 8.3 : Morris Mano, pg 368
ASM Timing Considerations Fig 8.3 Analysis • Clk cycle 1 • Present state = IDLE • Output AVAIL = 1 • Input START = 0 • NEXT Clk cycle (beginning of clk cycle 2 PGT) • Content of Reg A unchanged, AVAIL = 1, • Clk cycle 2 (PGT) • Present state = IDLE • START = 1 • NEXT Clk cycle (beginning of clk cycle 3 PGT) • Reg A = is cleared to 0 • Q(1:0) is examined = 01 • So path MUL1 is taken • Clk cycle 3 (PGT) • Present state = MUL1 • Reg A = 0
ASM Timing - Conclusion • Outputs appear while in the state (in response to state and input values) • Register transfers occur at the clock while exiting the state – So, new value occur in the next state!
