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Preliminary design of the SSLB (“S” for SLHC)

Preliminary design of the SSLB (“S” for SLHC). sLHC upgrade meeting. SLB – Functional Description. Overall synchronization of the ECAL and HCAL trigger primitives. Transmission of the Trigger Primitives to the Calorimeter Regional Trigger. SLB – Functional Description.

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Preliminary design of the SSLB (“S” for SLHC)

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  1. Preliminary design of the SSLB (“S” for SLHC) sLHCupgrade meeting

  2. SLB – Functional Description • Overall synchronization of the ECAL and HCAL trigger primitives. • Transmission of the Trigger Primitives to the Calorimeter Regional Trigger.

  3. SLB – Functional Description • Receives 9 bit data @ 40 MHz / TT • Each SLB houses 8 TT • Align Trigger Data using the LHC Orbit bunch structure to determine the BX position using internal histograms • FIFO stage to compensate fiber length differences, deserialisers lock delays and to guarantee the alignment of data sent to the RT from both ECAL and HCAL. • 2 TT data merging + Hamming code prior to send it over the high speed link • 4 High speed links (1.2Gb/s each)

  4. SSLB details • Maintain same connectivity and form factor • Replace cables by optical links • Latency budget increases in most cases when using FPGAs • High speed link, 850/1310 nm, commercial package • PCB for both ECAL/HCAL and RCT (duplex) • FPGA Transceivers, deeper FIFO and Full Orbit histogram per channel • Stratix II or IV (GX) or Virtex 4 or 5 (6 arriving) • SSLB (TX and RX)

  5. SYNC SYNC SYNC SYNC SYNC SYNC SYNC SYNC CLOCK Multiplier mux mux EDC EDC EDC EDC mux mux SSLB TPG side 4 x 8 Bit BUS 120.24 MHz Clock SYNC-S 4 x 9 BITS BUS 40.08 MHz HIGH SPEED MERGER 4.8GB/s Optical Transceiver PMC connectors SYNC-S 4 x 9 BITS BUS 40.08 MHz PMC connectors 120.24 MHz Clock, 15 ps jitter TTC BUS TTC_rx CLK SLB-S Controller (Embedded ) Local_BUS VITESSE ctrl interface RX_CLK Main Board Interface RX_BCO JTAG 90% JTAG Coverage

  6. CLOCK Multiplier DE MUX SSLB RCT side ALIGN DATA BLOCK PMC connectors 4.8GB/s Optical Transceiver RCT interface PMC connectors Controller (Embedded ) ctrl interface 90% JTAG Coverage

  7. SSLB PCB Preview

  8. SSLB borders EE EB EE EB borders EE-TCC: EB-TCC: EE-TCC: EB-TCC: SLB ABCD SLB CD SLB ABCD SLB AB Normal Cable 4x1.2Gb Hydra Cable 2x(2x1.2Gb) RCT Receiver Card RCT Receiver Card RCT Receiver Card

  9. SSLB PCB Preview

  10. Calorimeter Trigger Evolution Step 1 (2009) Step 2(2010-2011) Step 3 (>2011) Step 4 (>2012) ETCC:TPGs ETCC:TPGs HTR:TPGs ETCC:TPGs uTCA-HTR:TPGs ETCC:TPGs uTCA-HTR:TPGs uTCA-HTR:TPGs SLB SLB SLB SSLB SSLB SLB SLB RCT RCT SLB SSLB SSLB RCT SSLB RCT/ uTCA RCT/ uTCA Matrix& AuxCards  Cu GCT/uTCA GCT:Sources GCT:Sources GCT/uTCA GCT:Sources GCT/uTCA GCT/uTCA FO GCT:Main GT/GMT GT/GMT GT/GMT GT/GMT

  11. Calorimeter Trigger Evolution II Step 1 (2009) Step 2(2010-2011) Step 3 (>2011) Step 4 (>2012) ETCC:TPGs ETCC:TPGs HTR:TPGs ETCC:TPGs uTCA-HTR:TPGs ETCC:TPGs uTCA-HTR:TPGs uTCA-HTR:TPGs SLB SLB SLB SSLB SSLB SLB SLB RCT RCT SLB SSLB SSLB RCT SSLB RCT/ uTCA RCT/ uTCA Matrix& AuxCards  Cu GCT/uTCA GCT:Sources GCT:Sources GCT/uTCA GCT:Sources GCT/uTCA GCT/uTCA FO GCT:Main GT/GMT GT/GMT GT/GMT GT/GMT

  12. Conclusions • Use a single design for the new SLB , with Optical Transceivers • Both connectors footprints • Maintain modularity for compatibility with existing design • LIP will take the responsibility of this design

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