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Lecture 7: Instruction Set Architecture

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Lecture 7: Instruction Set Architecture

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  1. Lecture 7: Instruction Set Architecture Computer Engineering 585 Fall 2001

  2. Control Flow Instructions • Cond. Branches, jumps, procedure call/return • Branch instruction: while C do if C then for I=x to y do endwhile endif endfor eval C eval C I=x Br ¬C, +N Br ¬C, +N Br I==y, +N PC-relative Branches: PC+N

  3. Branch Taken inst1 branch0 R1 inst1 inst2 • 90% of the Loop branches taken. inst2 inst N branch0 R1 Backward-going branch Forward-going branch any loop -- for, while) (if-then-else)

  4. Frequency of Forward Branches 25% branches: backward 75% branches: forward Frequency of taken branches: 53% %Taken = (% Taken backward * % Backward) + (% Taken forward * % forward)

  5. Relative Frequency of Control Inst MIPS based measurements

  6. Branch Target Offset

  7. Branch Offset Size Branch offset: at least 8 bits Say 16 bit offset is supported --- target 24 bits away! Branch C, target Not-Taken code Branch ¬C, +2 Jump target Not-Taken code

  8. Gnd Result Condition Specification • Condition Code: Instructions set C,N,Z,V. • Condition Register: Two step process, one ALU inst. sets the condition register, and a branch checks it. • Compare & branch: Condition is part of branch instruction. Often comparison against 0. Register

  9. Branch Comparison Frequency

  10. Procedure calls/returns P1 P2 P3 • Where is the return address saved? an implicit dedicated register, or a GP register or a memory location. • For a register based machine, does P1 save the registers (caller-saving) or does P2 save them (callee-saving).

  11. Operand types • character: a byte; half-word: 2 bytes; word: 4 bytes; double-word: 8 bytes; single-precison FP: 4 bytes; double-precison FP: 8 bytes; character strings: one byte per char; packed decimal: one byte per two decimal digits. • How does an instruction know the operand type? • Add R1, R2, R3: Is R1 a byte or half-word or word? • Either instruction encodes this information: AddH: Add half-words or data carries a tag with it.

  12. Operand Distribution

  13. Operand Specification Opcode/#operands Addr Sp 1 Addr Field 1 Addr Sp n Addr Field n Opcode Addr 1 Addr 2 Addr 3 Addl3 R1, 1024(R2), (R3): 1 byte 1 byte 1+2 bytes 1 byte = 5 bytes

  14. Compiler Structure Front end High Level Optimizations Global Optimizations Code generator