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CSE 8383 - Advanced Computer Architecture. Week-3 Week of Jan 26, 2004 engr.smu.edu/~rewini/8383. Contents. Linear Pipelines Nonlinear pipelines Instruction Pipelines Arithmetic Operations Design of Multifunction Pipeline. Linear Pipeline. Processing Stages are linearly connected

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cse 8383 advanced computer architecture

CSE 8383 - Advanced Computer Architecture

Week-3

Week of Jan 26, 2004

engr.smu.edu/~rewini/8383

contents
Contents
  • Linear Pipelines
  • Nonlinear pipelines
  • Instruction Pipelines
  • Arithmetic Operations
  • Design of Multifunction Pipeline
linear pipeline
Linear Pipeline
  • Processing Stages are linearly connected
  • Perform fixed function
  • Synchronous Pipeline
    • Clocked latches between Stage i and Stage i+1
    • Equal delays in all stages
  • Asynchronous Pipeline (Handshaking)
latches
Latches

S1

S2

S3

L1

L2

Slowest stage determines delay

Equal delays  clock period

reservation table
Reservation Table

Time

S1

S2

S3

S4

non linear pipelines
Non Linear Pipelines
  • Variable functions
  • Feed-Forward
  • Feedback
linear instruction pipelines
Linear Instruction Pipelines
  • Assume the following instruction execution phases:
    • Fetch (F)
    • Decode (D)
    • Operand Fetch (O)
    • Execute (E)
    • Write results (W)
dependencies
Dependencies
  • Data Dependency

(Operand is not ready yet)

  • Instruction Dependency

(Branching)

Will that Cause a Problem?

data dependency
Data Dependency

I1 -- Add R1, R2, R3

I2 -- Sub R4, R1, R5

1

2

3

4

5

6

F

D

O

E

W

solutions
Solutions
  • STALL
  • Forwarding
  • Write and Read in one cycle
  • ….
instruction dependency
Instruction Dependency

I1 – Branch o

I2 –

1

2

3

4

5

6

F

D

O

E

W

solutions16
Solutions
  • STALL
  • Predict Branch taken
  • Predict Branch not taken
  • ….
floating point multiplication
Floating Point Multiplication
  • Inputs (Mantissa1, Exponenet1), (Mantissa2, Exponent2)
  • Add the two exponents  Exponent-out
  • Multiple the 2 mantissas
  • Normalize mantissa and adjust exponent
  • Round the product mantissa to a single length mantissa. You may adjust the exponent
linear pipeline for floating point multiplication
Linear Pipeline for floating-point multiplication

Round

Normalize

Add

Exponents

Multiply

Mantissa

Round

Normalize

Accumulator

Partial

Products

Add

Exponents

Re

normalize

linear pipeline for floating point addition
Linear Pipeline for floating-point Addition

Partial

Shift

Find

Leading 1

Add

Mantissa

Partial

Shift

Subtract

Exponents

Round

Re

normalize

combined adder and multiplier
Combined Adder and Multiplier

B

Partial

Products

G

C

H

F

A

Partial

Shift

Find

Leading 1

Add

Mantissa

Partial

Shift

Exponents

Subtract

/ ADD

Round

Re

normalize

E

D

nonlinear pipeline design
Nonlinear Pipeline Design
  • Latency

The number of clock cycles between two initiations of a pipeline

  • Collision

Resource Conflict

  • Forbidden Latencies

Latencies that cause collisions

nonlinear pipeline design cont
Nonlinear Pipeline Design cont
  • Latency Sequence

A sequence of permissible latencies between successive task initiations

  • Latency Cycle

A sequence that repeats the same subsequence

  • Collision vector

C = (Cm, Cm-1, …, C2, C1), m <= n-1

n = number of column in reservation table

Ci = 1 if latency i causes collision, 0 otherwise

collision vector for multiply after multiply
Collision Vector for Multiply after Multiply

Forbidden Latencies:1, 2

Collision vector

0 0 0 0 1 1  11

Maximum forbidden latency = 2  m = 2

example
Example

Y

X

S1

S2

S3

forbidden latencies
Forbidden Latencies
  • X after X
  • X after Y
  • Y after X
  • Y after Y
x after x
X after X

2

S1

S2

S3

5

S1

S2

S3

x after x34
X after X

4

S1

S2

S3

7

S1

S2

S3

collision vector
Collision Vector
  • Forbidden Latencies: 2, 4, 5, 7
  • Collision Vector =

1 0 1 1 0 1 0

y after y
Y after Y

S1

S2

S3

S1

S2

S3

collision vector37
Collision Vector
  • Forbidden Latencies: 2, 4
  • Collision Vector =

1 0 1 0

state diagram for x
State Diagram for X

8+

1 0 1 1 0 1 0

8+

3

8+

6

1*

1 0 1 1 0 1 1

1 1 1 1 1 1 1

3*

6

cycles
Cycles
  • Simple cycles each state appears only once

(3), (6), (8), (1, 8), (3, 8), and (6,8)

  • Greedy Cycles  simple cycles whose edges are all made with minimum latencies from their respective starting states

(1,8), (3)  one of them is MAL