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# We assume both adders are implemented with carry ripple adders. Every signal in - PowerPoint PPT Presentation

HA2. 1/2. a. Given is the following circuit. The input a is added in the first adder and subsequently in the second adder after multiplication by ½. 4. s. +. +. 4. We assume both adders are implemented with carry ripple adders. Every signal in

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1/2

a

Given is the following circuit.

The input a is added in the first adder

and subsequently in the second adder

after multiplication by ½.

4

s

+

+

4

We assume both adders are implemented with carry ripple adders. Every signal in

this example contains 4 bits and  represents the delay of the carry of the full adder.

The delay of the sum output equals 2.

1. Draw a bitlevel representation of this circuit.

2. How long is the critical path ?

3. What is the smallest possible critical path that can be be obtained by pipelining

or retiming ? What is the minimal number of flipflops ?

4. Can this circuit be speeded up by transformations ? How long is the critical path ?

What is the minimal number of flipflops ?

jvm