The 2002 ITRS Assembly and Packaging Roadmap Bill Chen - ASE

1. The 2002 ITRS Assembly and Packaging Roadmap Bill Chen - ASE

2. Joe Adam - Skyworks Mark Bird - Amkor Bill Bottoms - 3MTS Chi Shih Chang - K&S Bill Chen - ASE Ed Fulcher – LSI George Harman - NIST James Hayward - AMD Hisao Kasuga - NEC Mahadevan Iyer - IME Bernd Roemer - IFX Henry Utsunomiya Jurgen Wolf – IZM W.Y. Chen – ITRI Ted Zarbock – Intel Key ITRS Contributors

3. Compatibility Between Roadmaps • Focus participation of Jisso Roadmap members to co-ordinate inputs between regions and industry groups • Direct coordination with NEMI on packaging roadmap • Provide a general bridge through packaging to the electronic industry roadmap efforts

4. Market Sectors • Market Segments used in the roadmap historically are losing relevance due to changes in industry • NEMI is rewriting the market sectors in their 2002 revision • The new NEMI segments will be included in the 2003 ITRS update to keep the roadmaps aligned

5. Difficult Challenges Near Term • Tools and methodologies to address chip and package co-design • Chip and Package co-design and simulation (SI, Power, EMI), transient and localized hot spots - simulation of thermal mechanical stresses, thermal performance and current density in solder bumps • Improved Organic substrates • Increased wireability and dimensional control at low cost • Higher temperature stability and lower moisture absorption • Improved (or elimination of) underfills for flip chip • Improved underfill integration, adhesion, faster cure, higher temperature • Impact of Cu/low k on Packaging • Screening methods to evaluate compatibility of low K with packaging • Pb, Sb, and Br free materials at low cost • Technical approaches are well defined but cost is not in line with needs

6. Difficult Challenges Long Term • System level view to integrate chip, package, and system design • Design will be distributed across industry specialist • Very small die sizes with mid level I/O • Broadband application for high data rate (>10 Gbps) which requires new materials and design techniques • Package cost may greatly exceed die cost • Present R&D investments do not address this effectively

7. Changes to Requirements Tables • Wirebond pitch in the near term has been increased from last year • Substrate & other costs associated with finer pitch is limiting application • Peripheral flip chip pitch has been decreased significantly • Area array flip chip pitch has been increased in the short term but decreased in 2005 and beyond • Core Voltage level was reduced for certain market sectors. • Junction temperature for high performance and cost performance market sectors were increased in the near term.

8. Packaging Near Term Requirements

9. Packaging Near Term Requirements Table 79 Single Chip Packages Potential Solutions

10. Packaging Requirements Near Term

11. Packaging Requirements Long Term

12. Packaging Requirements Long Term

13. Issues to be addressed in 2003 • MEMS section will be expanded and will be addressed in the tables • Optoelectronics will be added to the tables • New materials impact and challenges will be expanded • Low k dielectric • High k dielectric • Pb, halogen and Sb free packaging • Cu metallization • Factory integration issues associated with under bump metal and wafer level packaging

14. Cross Cut Issues • Test • High frequency I/O for network applications increasing with the reduction in ESD protection levels need to understand this trade-off • MEMS and optoelectronics need to be address in 2003 test roadmap • Contact and handler requirements need to be linked to package pitches in 2003 • Modeling • Thermal/mechanical simulation of low K package interactions to predict failures and understand new failure mechanisms • We will set-up point people in each TWG to work the cross-cuts • Research needed in applied math to improve simulations • EHS • Will set-up a focused team for 2003 to address the roadmap for Pb Free Long term requirements • Water usage in substrate manufacturing

15. Cross Cut Issues • Interconnect • Low K and Cu interaction with packaging added 2003 • Design & PIDS • High frequency I/O for network applications increasing with the reduction in ESD protection levels need to understand this trade-off • Factory Integration • Wafer level test and packaging and under bump metal are blurring the boundary between fab and assembly. Factory integration will add packaging section to the 2003 revision • Wafer and die tracking through the assembly process needs to be defined and standardized

16. Conclusions • The importance of Packaging in electronics will grow dramatically over the next 15 years based on the changing economics of the industry • The technical challenges are being broader in scope and more complex requiring in increase in skill and investment • The interdependence between packaging and other major technology areas in the electronics supply chain is increasing quickly • Companies will succeed or fail based on packaging and test capabilities