CS M51A/EE M16 Winter’05 Section 1 Logic Design of Digital Systems Lecture 7

1. W’05 CS M51A/EE M16 Winter’05 Section 1 Logic Design of Digital SystemsLecture 7 February 2 Yutao He yutao@cs.ucla.edu 4532B Boelter Hall http://courseweb.seas.ucla.edu/classView.php?term=05W&srs=187154200

2. Outline • Chapter Wrap-up: Programmable modules • Chapter 6: Multiple-Level Networks • Summary

3. Design in Two-Level Logic - Review • Basic Technology: • AND-OR, OR-AND, NAND-NAND, NOR-NOR • Programmable modules • PLAs • PALs • Basic Skills: • K-Map • Don’t cares • Minterms • Maxterms • Quine-McCluskey Algorithm • Boolean Algebra

4. Design with Programmable Modules • Regular and standard structure • Customized (programmed) for a particular function • During the last stage of fabrication • When incorporated into a system • Flexible use and field upgrade • Slower than fixed-function modules • Common types: • PLAs • PALs • CPLDs • FPGAs

5. inputs • • • ORArray productterms ANDArray • • • • • • PLA (n, p, m) outputs Programmable Logic Arrays (PLAs) • Pre-fabricated building block of many AND/OR gates • ”Programmed" by making or breaking connections among gates • Programmable array block diagram for sum of products form

6. Logic Diagram of PLAs • All possible connections available before "programming"

7. Alternative Representation • Short-hand notation - don't have to draw all the wires

8. How to design with PLAs • Step 1: • Obtain the minimal AND-OR (Product-Of-Sum) expression of a function • Step 2: • Construct the personality matrix • Step 3: • Make connections on the logic diagram by placing a big dot at the corresponding cross-point.

9. personality matrix product inputs outputs term A B C F0 F1 F2 F3AB 1 1 – 0 1 1 0B'C – 0 1 0 0 0 1AC' 1 – 0 0 1 0 0B'C' – 0 0 1 0 1 0A 1 – – 1 0 0 1 F0 F1 F2 F3 reuse of terms Design with PLAs - Example A B C F0 = A + B' C' F1 = A C' + A B F2 = B' C' + A B F3 = B' C + A

10. Programmable Array Logic (PAL) • Each OR gate is connected to a subset of the AND gates

11. Minimization of Multi-Output Functions • Basic idea: • Separate each output function and minimize them individually • Find out whether there is any common terms (product or sum) and share them if so.

12. Two-Level Logic - Limitations • One extra level is required if the complemented form of an input is not available • Existing technologies limit the maximal number of inputs (fan-ins) of a gate • Two-level implementation may require a large number of gates and an irregular structure • The cost criteria of minimization is not adequate for many MSI/LSI/VLSI designs

13. Design Using Multi-Level Logic • Motivation: • To satisfy constraints: • network size • number of gate inputs • network delay • Challenges: • No canonical form is available • Several requirements have to be met simultaneously • Several outputs have to be considered • In reality, software CAD tools are used which employ heuristic algorithms to perform the minimization (Logic Synthesis)

14. Design Procedure with Multi-Level Logic • Step 1: • Obtain AND-OR or OR-AND expressions of switching functions of the system • Step 2: • Transform expressions such that requirements are met • Step 3: • Replace AND/OR gates with NAND or NOR gates whenever appropriate • Several iterations may be needed

15. Typical Transformation Techniques • To reduce the network size: • Factoring • ab+ac = a(b+c) • Sharing • y = ab+bc, z = a’b+bc • Use other types of gates with small size • XOR gates, etc. • To reduce the fan-in of a gate: • term decomposition • a + b + c + d = (a+b) + (c+d) • abcd = (ab)(cd) • To increase the output load of a gate: • Buffering

16. Eg. 1 - 1-bit Comparator

17. Encoding Scheme: Truth Table: 1-bit Comparator (Cont’d)

18. Switching Expressions: 1-bit Comparator (Cont’d) Two-Level Networks: - 7 AND gates - 4 OR gates - 22 equivalent gates - 25 gate inputs

19. 1-bit Comparator (Cont’d) • Applying transformation techniques: • z2 = xy’+xc2+y’c2 = xy’+(x+y’)c2 • z1 = (x’+y)(x+y’)c1 • z0 = x’y+(x’+y)c0 • Shared terms: • x+y’, x’+y • Size: • 5 AND gates • 4 OR gates • 18 equivalent gates

20. 1-bit Comparator (Cont’d) • Further Reduction: • Using NAND gates • Size: • 9 equivalent gates

21. Two-Level Expressions: Eg. 2 - Modulo-64 Incrementer Two-Level Networks: - 7 NOT gates - 20 AND gates - 5 OR gates - 77 gate inputs

22. Applying the decomposition technique: Multi-level expressions: Modulo-64 Incrementer (Cont’d)

23. Modulo-64 Incrementer (Cont’d)

24. Eg. 3 - Enabling Circuit

25. Enabling Circuit (Cont’d)

26. x z x0 y 0 1 3 2 4 5 7 6 x2 12 13 15 14 8 9 11 10 x0 x3 x0 X Y Z0 0 00 1 11 0 1 1 1 0 0 1 1 0 0 1 1 0 0 1 2 3 0 1 3 2 4 5 7 6 0 1 1 0 0 1 1 0 x1 0 1 1 0 x2 x1 0 1 1 0 0 1 1 0 x1 Design Using XOR Gates • XOR Gates: • Exclusive OR, difference • z = x  y = xy’+x’y • Can be generalized into n inputs

27. Eg. 5 - Parity-Checking Circuit • Concept • Error detection codes • Additional bits are added for checking data bits • Used extensively in data communication and storage • Types: • Even: • The number of 1s is even • Odd • The number of 1s is odd Data: 0010 0001 Even: 0010 0001 Odd: 0010 0001 0 1

28. 8-Input Odd-Parity Checking Circuit • High-Level Specification: • Two-Level AND-OR Implementation: • Too many gates

29. Odd-Parity Checking Circuit (Cont’d) • Design with XOR gates: • How to design an even-parity checking circuit using XOR gates?

30. Eg. 7 - 32-bit Equality Comparator • High-Level Specification: • Two-Level Implementation:

31. 32-bit Equality Comparator (Cont.)

32. Summary • Programmable Modules • PLAs and PALs • Design combinational circuits using multi-level gate networks

33. Next Lecture • Chapter 4 – Analysis of Combinational Networks