HyperTransport™ Technology I/O Link. Presentation by Mike Jonas. The I/O Bandwidth Problem. While microprocessor performance continues to double every eighteen months, the performance of the I/O bus architecture has lagged, doubling in performance approximately every three years.
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Presentation by Mike Jonas
A number of new technologies are responsible for the increasing demand for additional bandwidth.
Improve system performance
- Provide increased I/O bandwidth
- Ensure low latency responses
- Reduce power consumption
Simplify system design
- Use as few pins as possible to allow smaller packages and to reduce cost
Increase I/O flexibility
- Provide a modular bridge architecture
Maintain compatibility with legacy systems
- Complement standard external buses
- Have little or no impact on existing operating systems and drivers
Ensure extensibility to new system network architecture (SNA) buses
Provide highly scalable multiprocessing systems
HyperTransport technology creates a packet-based link implemented on two independent, unidirectional sets of signals. It provides a broad range of system topologies built with three generic device types:
It would seem at a glance that they failed in their objective of lowering pin count because they require 2 pins per bit of data being transferred per direction. Why then do they claim to have reduced pin count? The increase in signal pins is offset by three factors:
PCI Express also uses LVDS
Each data lane of a PCI Express card transmits 250 Mbytes/s in each direction.
As shown here an 8 lane PCI express connector has 49 total pins
- All 16-bit, 32-bit, and asymmetrically-sized configurations must be enabled by a software initialization step.
- After a cold reset BIOS reprograms all linked to the desired width
- At cold reset, all links power-up with 200-MHz clocks.
- Registers store supported clock frequencies
- After some analysis Firmware then writes the two frequency registers to set the frequency for each link.
- Once all devices have been configured, firmware initiates an LDTSTOP# disconnect or RESET# of the affected chain to cause the new frequency to take effect.