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ITRS Roadmap Design + System Drivers 2006 Spring Meeting Vaals, April 6-7 Worldwide Design TWG

ITRS Roadmap Design + System Drivers 2006 Spring Meeting Vaals, April 6-7 Worldwide Design TWG. 2006 Agenda. DESIGN Improve tables: based on feedback, industry data Discuss additions: SW (System-level) PIDS and yield connections (DFM) SYSTEM DRIVERS Discuss status of new drivers

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ITRS Roadmap Design + System Drivers 2006 Spring Meeting Vaals, April 6-7 Worldwide Design TWG

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  1. ITRS Roadmap Design + System Drivers2006 Spring MeetingVaals, April 6-7Worldwide Design TWG

  2. 2006 Agenda • DESIGN • Improve tables: • based on feedback, industry data • Discuss additions: • SW (System-level) • PIDS and yield connections (DFM) • SYSTEM DRIVERS • Discuss status of new drivers • (consumer, network, auto/industrial) • Discuss update of existing drivers • Discuss alignment with PIDS/NEMI/etc.

  3. Key Thoughts • Last year we found Design is connected with TWGs • General dependency: PIDS, yield, interconnect, A&P,… • This year we’re finding System Drivers are too! • Specific dependency: PIDS, interconnect, A&P,… • New drivers are being developed in 2006 • Consumer stationary, networking, auto • Emerging challenges and techniques in most drivers • Multi-core and leakage changes everything

  4. 2006 Design

  5. Working Table For Design Chapter

  6. System Drivers Chapter

  7. ITRS-iNEMI Domain Space iNEMI (emulators) Market requirements ITRS (Drivers) Tech requirements Chip level System level

  8. Technology Waves And (VC) Investment Digital Bio Medical Cleantech Digital media Emerging Geos Consumer $20+B /year Internet Telco Enterprise PC/ Client/ server $5+B /year Mainframe / Mini 70s 80s 90s 2000s 2010s Source: insight from Top VCs including Walden

  9. 4. System Drivers “Matrix” Alignment Fabrics MPU 2006 PE(DSP) Memory AMS Medical Automotive Office Network Defense [Industrial] Consumer/ Portable Markets

  10. Drivers Starting To Drive Roadmap Downstream components Interconnect A&P Power Performance Bandwidth Area Driver Driver Driver Driver Fabric Driver Design requirements And solutions Fabric Fabric Canonical block Canonical block Canonical block Canonical block Nominal parameters Variation/distribution Upstream components PIDS Modeling

  11. Driver Template

  12. System (Market) Drivers Working Table

  13. Process For Each System Driver Industry data Synch with iNEMI market emulators 1 Select Critical/difficult parameters Select DRIVER requirements Identify market requirements 3 2 Cost Perf. Identify design requirements Create model Generate data Color data Identify key design parameters #units Size per unit Memory Pins Power Area Hrs. operation Power Market Drivers Table

  14. System Drivers Possible ITRS-iNEMI Engagement Model

  15. Generic features of “SOC Consumer Stationary” Contrast with “SOC Consumer Portable” Main Processor IO - Memory IF & Chip-to-Chip IF - Main Processor DPE DPE DPE DPE Main Memory PE PE PE DPE DPE DPE DPE PE PE PE Main Processor DPE DPE DPE DPE PE PE PE Peripherals PE PE PE Function A Function B Function C DPE DPE DPE DPE Function D Function E PE PE

  16. Design Trend: # of Processors & Processing Performance Max Processing Performance [TFLOPS]

  17. Channel A Networking Driver Transmitter core Receiver core High-bandwidth host chip High-bandwidth switch chip

  18. Chip Structure I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O • Very high bandwidth • Key driver • Large size • Many high-speed I/Os • Mixed signal • Consume lots of power • Key components • I/O • Switch fabric • Possible control processor and memory • CMOS technology Switch Fabric Peripherals Processor Memory Memory I/O?

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