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Virtual Memory

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  1. Virtual Memory

  2. DRAM as cache • What about programs larger than DRAM? • When we run multiple programs, all must fit in DRAM! • Add another larger, slower level to the memory hierarchy - use part of the hard drive.

  3. Virtual Memory • Memory Size - • Protection -

  4. Virtual Memory • Memory Size - allows total memory allocation to exceed DRAM capacity. • Protection -

  5. Virtual Memory • Memory Size - allows total memory allocation to exceed DRAM capacity. • Protection - programs may not access each other’s memory.

  6. Multi-Processing - no VM Prog A • Program A begins

  7. Multi-Processing - no VM Prog A • Program A begins • Program B begins Prog B What happens if A wants more memory?

  8. Multi-Processing - no VM Prog A • Program A begins • Program B begins Prog B What happens if A wants more memory? Out of luck. If we gave A memory after the end of B, then A would be able to access all of B’s memory.

  9. Multi-Processing - no VM • Program A begins • Program B begins • Program A ends Prog B

  10. Multi-Processing - no VM • Program A begins • Program B begins • Program A ends • Program C ready Prog C Prog B

  11. Multi-Processing - no VM • Program A begins • Program B begins • Program A ends • Program C ready • It can not run even though there is enough free space • Fragmentation Prog C Prog B

  12. Virtual Memory • Use hard drive to storerunning programs and use DRAM on demand • Allocate memory in pages • Provide protection by page

  13. Address Space • Virtual Address Space • Physical Address Space

  14. Address Space • Virtual Address Space • Located on Hard Drive (essentially) • Starts at 0 for each program • Physical Address Space

  15. Address Space • Virtual Address Space • Located on Hard Drive (essentially) • Starts at 0 for each program • Physical Address Space • Located in DRAM • The “cache” for the Hard Drive

  16. Hard Drive Multi-Processing - VM Virtual Address Physical Address 0 Prog A • Program A begins • Program B begins 16K

  17. Hard Drive Multi-Processing - VM Virtual Address Physical Address 0 Prog A • Program A begins • Program B begins 16K 0 Prog B 24K

  18. Multi-Processing - VM Virtual Address Physical Address 0 Prog A • Program A begins • Program B begins 16K What happens if A wants more memory? 0 Prog B 24K Hard Drive

  19. Hard Drive Multi-Processing - VM Virtual Address Physical Address 0 Prog A • Program A begins • Program B begins 20K What happens if A wants more memory?Allocate another virtual page. 0 Prog B 24K

  20. Hard Drive Multi-Processing - VM Virtual Address Physical Address • Program A begins • Program B begins • Program A ends 0 Prog B 24K

  21. Hard Drive Multi-Processing - VM Virtual Address 0 Physical Address Prog C • Program A begins • Program B begins • Program A ends • Program C begins • Not all placed in DRAM • DRAM use need not be contiguous 28K 0 Prog B 24K

  22. Virtual Memory is like caching… • _______ is the cache for the __________ • It contains only a subset of the total space • Given an address, determine whether it is currently in the “cache” • On a miss, obtain data and place in “cache”

  23. Virtual Memory is like caching… • DRAM is the cache for the hard drive • It contains only a subset of the total space • Given an address, determine whether it is currently in the “cache” • On a miss, obtain data and place in “cache”

  24. Virtual Memory is not like caching… • The miss penalty is orders of magnitude larger than for the cache • You must know where it resides in DRAM before you can look it up in L1 cache • This leads to a much different implementation

  25. The Search • Cache – search each block in set for the proper tag • Virtual Memory – store a table that is a mapping from virtual address to physical location (DRAM location).

  26. Virtual Memory Implementation • Programs use virtual addresses • VM Block is called a __________ • A VM DRAM “cache miss” is called a ______________. • To access data, the address must translate it to a _______________. • This translation is called _______________ or ________________.

  27. Virtual Memory Implementation • Programs use virtual addresses • VM Block is called a page • A VM DRAM “cache miss” is called a ______________. • To access data, the address must translate it to a _______________. • This translation is called _______________ or ________________.

  28. Virtual Memory Implementation • Programs use virtual addresses • VM Block is called a page • A VM DRAM “cache miss” is called a page fault. • To access data, the address must translate it to a _______________. • This translation is called _______________ or ________________.

  29. Virtual Memory Implementation • Programs use virtual addresses • VM Block is called a page • A VM DRAM “cache miss” is called a page fault. • To access data, the address must translate it to a _physical address_. • This translation is called _______________ or ________________.

  30. Virtual Memory Implementation • Programs use virtual addresses • VM Block is called a page • A VM DRAM “cache miss” is called a page fault. • To access data, the address must translate it to a _physical address_. • This translation is called memory mapping_ or _virtual to physical translation.

  31. Virtual Memory Implementation • Translation process: • Why is Physical address smaller than Virtual? Virtual page number Page offset Translation Physical page number Page offset

  32. Virtual Memory Implementation • Translation process: • Why is Physical address smaller than Virtual? DRAM is the cache – should be smaller than the total virtual address space Virtual page number Page offset Translation Physical page number Page offset

  33. Virtual Memory ImplementationPage faults incredibly costly • DRAM is a cache - • Direct-mapped? • Set-associative? • Fully associative? • Low associativity • miss rate, search time • High associativity • miss rate, search time

  34. Virtual Memory ImplementationPage faults incredibly costly • DRAM is a cache - • Direct-mapped? • Set-associative? • Fully associative? • Low associativity • high miss rate, low search time • High associativity • low miss rate, high search time

  35. Virtual Memory ImplementationPage faults incredibly costly • DRAM is a cache - • Direct-mapped? • Set-associative? • Fully associative? • Low associativity • high miss rate, low search time • High associativity • low miss rate, high search time Access time: ~50 cycles + search, miss penalty: hundreds of cycles

  36. Virtual Memory ImplementationPage fault incredibly costly • DRAM is a cache - • Direct-mapped? • Set-associative? • Fully associative!!!! • Low associativity • high miss rate, low search time • High associativity • low miss rate, high search time Access time: ~50 cycles + search, miss penalty: thousand? cycles

  37. Virtual Memory ImplementationPage fault incredibly costly • Fully associative!!!! • Large block size (4KB-16KB) • Sophisticated software to implement replacement policy • updates are hidden under page fault penalty • Definitely NOT write-through - only write-back.

  38. Translation • Does the same virtual address (in all processes) always translate to the same physical address (at one moment in time)? • How often does a translation occur?

  39. Translation • Does the same virtual address always translate to the same physical address? • No - each process has same Virtual addresses • How often does a translation occur?

  40. Translation • Does the same virtual address always translate to the same physical address? • No - each process has same Virtual addresses • Store translations in process page table • How often does a translation occur?

  41. Translation • Does the same virtual address always translate to the same physical address? • No - each process has same Virtual addresses • Store translations in process page table • How often does a translation occur? • At least once per instruction

  42. Translation • Does the same virtual address always translate to the same physical address? • No - each process has same Virtual addresses • Store translations in process page table • How often does a translation occur? • At least once per instruction • Need to perform translation quickly • Cache recent translations!

  43. Translation • Maintaining per process page tables • Process page table maintained by ____ - ___________________________ • Making translations fast • Use a TLB (__________________________) to cache recent translations • Fully associative but ____________________

  44. Translation • Maintaining per process page tables • Process page table maintained by OS - some pinned into DRAM • Making translations fast • Use a TLB (__________________________) to cache recent translations • Fully associative but ___________________

  45. Translation • Maintaining per process page tables • Process page table maintained by OS - some pinned into DRAM • Making translations fast • Use a TLB (Translation Lookaside Buffer) to cache recent translations • Fully associative but ___________________

  46. Translation • Maintaining per process page tables • Process page table maintained by OS - some pinned into DRAM • Making translations fast • Use a Translation Lookaside Buffer (TLB) to cache recent translations • Fully associative but very small - 16-64 entries

  47. Step 1: TLB • Search all locations of TLB in parallel (fully-associative) Virtual page number Page offset VPN PPN Physical page number Page offset

  48. Step 1: TLB • Search all locations of TLB in parallel • Hit - • Miss -

  49. Step 1: TLB • Search all locations of TLB in parallel • Hit - return address, proceed with memory access • Miss -

  50. Step 1: TLB • Search all locations of TLB in parallel • Hit - return address, proceed with memory access • Miss - retrieve translation from process page table –