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The Design Of A Differential CMOS Charge Pump For High Performance Phase-Locked-Loops

The Design Of A Differential CMOS Charge Pump For High Performance Phase-Locked-Loops. 班級：積體所碩一 學生：林欣緯 指導教授：林志明 教授. Bortecene Terlemez and John P. Uyemura ISCAS2004. Outline. Introduction Charge Pump Architecture Simulation Results PLL Test Result Conclusion. Introduction.

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The Design Of A Differential CMOS Charge Pump For High Performance Phase-Locked-Loops

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  1. The Design Of A Differential CMOS Charge Pump For High Performance Phase-Locked-Loops 班級：積體所碩一 學生：林欣緯 指導教授：林志明 教授 Bortecene Terlemez and John P. Uyemura ISCAS2004

  2. Outline • Introduction • Charge Pump Architecture • Simulation Results • PLL Test Result • Conclusion

  3. Introduction • Fundamentally, an ideal charge pump combined with an ideal PFD provides an unbounded pull-in range (limited by the oscillator’s frequency range) and zero static phase error in charge pump PLLs.

  4. Conventional single ended charge pump model

  5. The requirements for an effective charge pump • Equal charge/discharge current at any charge pump output voltage. • Minimal charge injection into the output node. • Minimal charge sharing between the output node and any floating node.

  6. Improved single ended charge pump circuit get rid of floating nodes to remove the charge-sharing problem

  7. Differential output generation

  8. Common-modefeedback scheme

  9. Common-modefeedback circuit

  10. Layout for the differentialcharge pump

  11. Phase-frequencydetector schematics

  12. Differential charge pump operation

  13. Charge pump outputlinear range 1.07 V/output

  14. Phase-locked stateat fVCO= 2.5 GHz

  15. Measured phase noiseof the 1/16 output

  16. PLL Performance Summary

  17. Conclusion • achieve low charge sharing and low charge injection in low voltage PLL applications. • the output voltage range of the charge pump is increased while charging/discarging current matching is realized.

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