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2010 - 0.13um Test Chip Early Results

This study presents early results of a test chip evaluating VDC pre-emphasis techniques for enhanced high-speed data transmission. The chip includes VDC with pre-emphasis, CML driver, fixed and multi-speed DORIC modules. Testing at various speeds, such as 5Gb/s and 160Mb/s, highlighted the effectiveness of pre-emphasis in improving signal quality. The chip design, spare channel configurations, recovered clock/data performance, and bit error rate thresholds are explored. Images of the VDC under test and DORIC modules are included.

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2010 - 0.13um Test Chip Early Results

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  1. 2010 - 0.13um Test ChipEarly Results D.S.S. 6/8/2010

  2. Chip and Contents VDC Spare Channel VDC VDC with Pre-Emphasis VDC with Pre-Emphasis CML Driver with Pre-Emphasis Fixed Speed DORIC (40Mb/s) Fixed Speed DORIC (40M/s) Fixed Speed DORIC (40Mb/s) Multi Speed DORIC / Spare Design Photo

  3. VDC Under Test (photo) • Test Card • Fiber Positioning Stage

  4. Pre-emphasis VDC at 5Gb/s

  5. Pre-emphasis VDC at 4.8Gb/s

  6. Pre-emphasis VDC at 4Gb/s

  7. Pre-emphasis VDC at 160 Mb/s

  8. VDC at 5Gb/s

  9. VDC at 4.8Gb/s

  10. VDC at 4Gb/s

  11. VDC at 160Mb/s

  12. Spare VDC @ 4G (from 1)

  13. Spare VDC @ 4G (from 2)

  14. Spare VDC @ 4G (from 3)

  15. Spare VDC @ 4G (from self)

  16. DORIC Under Test (Photo) • Test Card

  17. DORIC Recovered Clock / Data @ 40Mb/s

  18. DORIC Recovered Clock / Data @ 80Mb/s

  19. DORIC Recovered Clock / Data @ 160Mb/s

  20. DORIC Recovered Clock / Data @ 320Mb/s

  21. Doric Pk-Pk Clock Jitter • 40Mb/s • 80Mb/s • 160Mb/s • 320Mb/s

  22. DORIC BER Threshold

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